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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) by DM4PR11MB6068.namprd11.prod.outlook.com (2603:10b6:8:64::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8398.24; Fri, 7 Feb 2025 16:22:33 +0000 Received: from PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350]) by PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350%7]) with mapi id 15.20.8422.012; Fri, 7 Feb 2025 16:22:33 +0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In-Reply-To: <20250206192148.53610-3-gustavo.sousa@intel.com> References: <20250206192148.53610-1-gustavo.sousa@intel.com> <20250206192148.53610-3-gustavo.sousa@intel.com> Subject: Re: [PATCH 2/3] drm/i915/display: Use display-specific platform checks in intel_bw.c From: Gustavo Sousa To: , Date: Fri, 7 Feb 2025 13:22:28 -0300 Message-ID: <173894534825.1963.9135467857710590685@intel.com> User-Agent: alot/0.12.dev27+gd21c920b07eb X-ClientProxiedBy: MW4PR04CA0301.namprd04.prod.outlook.com (2603:10b6:303:82::6) To PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8287:EE_|DM4PR11MB6068:EE_ X-MS-Office365-Filtering-Correlation-Id: d0472474-aab5-4db2-e8d2-08dd4793a031 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014; 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> u32 val =3D 0, val2 =3D 0; > u16 dclk; > int ret; >@@ -89,7 +90,7 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915= _private *dev_priv, > return ret; >=20 > dclk =3D val & 0xffff; >- sp->dclk =3D DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv)= >=3D 12 ? 500 : 0), >+ sp->dclk =3D DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(display) = >=3D 12 ? 500 : 0), > 1000); > sp->t_rp =3D (val & 0xff0000) >> 16; > sp->t_rcd =3D (val & 0xff000000) >> 24; >@@ -155,7 +156,7 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_priv= ate *dev_priv, > struct intel_display *display =3D &dev_priv->display; > int ret; >=20 >- if (DISPLAY_VER(dev_priv) >=3D 14) >+ if (DISPLAY_VER(display) >=3D 14) > return 0; >=20 > /* bspec says to keep retrying for at least 1 ms */ >@@ -206,9 +207,11 @@ intel_read_qgv_point_info(struct drm_i915_private *de= v_priv, > struct intel_qgv_point *sp, > int point) > { >- if (DISPLAY_VER(dev_priv) >=3D 14) >+ struct intel_display *display =3D &dev_priv->display; >+ >+ if (DISPLAY_VER(display) >=3D 14) > return mtl_read_qgv_point_info(dev_priv, sp, point); >- else if (IS_DG1(dev_priv)) >+ else if (display->platform.dg2) Woops... This should have been display->platform.dg1. That would explain the -EINVAL that we see in BAT results for DG1. I'll recheck for other typos and send a v2. -- Gustavo Sousa > return dg1_mchbar_read_qgv_point_info(dev_priv, sp, point= ); > else > return icl_pcode_read_qgv_point_info(dev_priv, sp, point)= ; >@@ -218,13 +221,14 @@ static int icl_get_qgv_points(struct drm_i915_privat= e *dev_priv, > struct intel_qgv_info *qi, > bool is_y_tile) > { >+ struct intel_display *display =3D &dev_priv->display; > const struct dram_info *dram_info =3D &dev_priv->dram_info; > int i, ret; >=20 > qi->num_points =3D dram_info->num_qgv_points; > qi->num_psf_points =3D dram_info->num_psf_gv_points; >=20 >- if (DISPLAY_VER(dev_priv) >=3D 14) { >+ if (DISPLAY_VER(display) >=3D 14) { > switch (dram_info->type) { > case INTEL_DRAM_DDR4: > qi->t_bl =3D 4; >@@ -252,7 +256,7 @@ static int icl_get_qgv_points(struct drm_i915_private = *dev_priv, > MISSING_CASE(dram_info->type); > return -EINVAL; > } >- } else if (DISPLAY_VER(dev_priv) >=3D 12) { >+ } else if (DISPLAY_VER(display) >=3D 12) { > switch (dram_info->type) { > case INTEL_DRAM_DDR4: > qi->t_bl =3D is_y_tile ? 8 : 4; >@@ -267,7 +271,7 @@ static int icl_get_qgv_points(struct drm_i915_private = *dev_priv, > qi->deinterleave =3D is_y_tile ? 1 : 2; > break; > case INTEL_DRAM_LPDDR4: >- if (IS_ROCKETLAKE(dev_priv)) { >+ if (display->platform.rocketlake) { > qi->t_bl =3D 8; > qi->max_numchannels =3D 4; > qi->channel_width =3D 32; >@@ -286,7 +290,7 @@ static int icl_get_qgv_points(struct drm_i915_private = *dev_priv, > qi->max_numchannels =3D 1; > break; > } >- } else if (DISPLAY_VER(dev_priv) =3D=3D 11) { >+ } else if (DISPLAY_VER(display) =3D=3D 11) { > qi->t_bl =3D dev_priv->dram_info.type =3D=3D INTEL_DRAM_D= DR4 ? 4 : 8; > qi->max_numchannels =3D 1; > } >@@ -491,16 +495,16 @@ static int tgl_get_bw_info(struct drm_i915_private *= dev_priv, const struct intel > return ret; > } >=20 >- if (DISPLAY_VER(dev_priv) < 14 && >+ if (DISPLAY_VER(display) < 14 && > (dram_info->type =3D=3D INTEL_DRAM_LPDDR4 || dram_info->type = =3D=3D INTEL_DRAM_LPDDR5)) > num_channels *=3D 2; >=20 > qi.deinterleave =3D qi.deinterleave ? : DIV_ROUND_UP(num_channels= , is_y_tile ? 4 : 2); >=20 >- if (num_channels < qi.max_numchannels && DISPLAY_VER(dev_priv) >= =3D 12) >+ if (num_channels < qi.max_numchannels && DISPLAY_VER(display) >= =3D 12) > qi.deinterleave =3D max(DIV_ROUND_UP(qi.deinterleave, 2),= 1); >=20 >- if (DISPLAY_VER(dev_priv) >=3D 12 && num_channels > qi.max_numcha= nnels) >+ if (DISPLAY_VER(display) >=3D 12 && num_channels > qi.max_numchan= nels) > drm_warn(&dev_priv->drm, "Number of channels exceeds max = number of channels."); > if (qi.max_numchannels !=3D 0) > num_channels =3D min_t(u8, num_channels, qi.max_numchanne= ls); >@@ -591,7 +595,7 @@ static int tgl_get_bw_info(struct drm_i915_private *de= v_priv, const struct intel > static void dg2_get_bw_info(struct drm_i915_private *i915) > { > struct intel_display *display =3D &i915->display; >- unsigned int deratedbw =3D IS_DG2_G11(i915) ? 38000 : 50000; >+ unsigned int deratedbw =3D display->platform.dg2_g11 ? 38000 : 50= 000; > int num_groups =3D ARRAY_SIZE(display->bw.max); > int i; >=20 >@@ -737,7 +741,7 @@ static unsigned int icl_qgv_bw(struct drm_i915_private= *i915, > struct intel_display *display =3D &i915->display; > unsigned int idx; >=20 >- if (DISPLAY_VER(i915) >=3D 12) >+ if (DISPLAY_VER(display) >=3D 12) > idx =3D tgl_max_bw_index(i915, num_active_planes, qgv_poi= nt); > else > idx =3D icl_max_bw_index(i915, num_active_planes, qgv_poi= nt); >@@ -750,24 +754,26 @@ static unsigned int icl_qgv_bw(struct drm_i915_priva= te *i915, >=20 > void intel_bw_init_hw(struct drm_i915_private *dev_priv) > { >- if (!HAS_DISPLAY(dev_priv)) >+ struct intel_display *display =3D &dev_priv->display; >+ >+ if (!HAS_DISPLAY(display)) > return; >=20 >- if (DISPLAY_VERx100(dev_priv) >=3D 1401 && IS_DGFX(dev_priv)) >+ if (DISPLAY_VERx100(display) >=3D 1401 && display->platform.dgfx) > xe2_hpd_get_bw_info(dev_priv, &xe2_hpd_sa_info); >- else if (DISPLAY_VER(dev_priv) >=3D 14) >+ else if (DISPLAY_VER(display) >=3D 14) > tgl_get_bw_info(dev_priv, &mtl_sa_info); >- else if (IS_DG2(dev_priv)) >+ else if (display->platform.dg2) > dg2_get_bw_info(dev_priv); >- else if (IS_ALDERLAKE_P(dev_priv)) >+ else if (display->platform.alderlake_p) > tgl_get_bw_info(dev_priv, &adlp_sa_info); >- else if (IS_ALDERLAKE_S(dev_priv)) >+ else if (display->platform.alderlake_s) > tgl_get_bw_info(dev_priv, &adls_sa_info); >- else if (IS_ROCKETLAKE(dev_priv)) >+ else if (display->platform.rocketlake) > tgl_get_bw_info(dev_priv, &rkl_sa_info); >- else if (DISPLAY_VER(dev_priv) =3D=3D 12) >+ else if (DISPLAY_VER(display) =3D=3D 12) > tgl_get_bw_info(dev_priv, &tgl_sa_info); >- else if (DISPLAY_VER(dev_priv) =3D=3D 11) >+ else if (DISPLAY_VER(display) =3D=3D 11) > icl_get_bw_info(dev_priv, &icl_sa_info); > } >=20 >@@ -782,8 +788,8 @@ static unsigned int intel_bw_crtc_num_active_planes(co= nst struct intel_crtc_stat >=20 > static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state= *crtc_state) > { >+ struct intel_display *display =3D to_intel_display(crtc_state); > struct intel_crtc *crtc =3D to_intel_crtc(crtc_state->uapi.crtc); >- struct drm_i915_private *i915 =3D to_i915(crtc->base.dev); > unsigned int data_rate =3D 0; > enum plane_id plane_id; >=20 >@@ -797,7 +803,7 @@ static unsigned int intel_bw_crtc_data_rate(const stru= ct intel_crtc_state *crtc_ >=20 > data_rate +=3D crtc_state->data_rate[plane_id]; >=20 >- if (DISPLAY_VER(i915) < 11) >+ if (DISPLAY_VER(display) < 11) > data_rate +=3D crtc_state->data_rate_y[plane_id]; > } >=20 >@@ -807,10 +813,9 @@ static unsigned int intel_bw_crtc_data_rate(const str= uct intel_crtc_state *crtc_ > /* "Maximum Pipe Read Bandwidth" */ > static int intel_bw_crtc_min_cdclk(const struct intel_crtc_state *crtc_st= ate) > { >- struct intel_crtc *crtc =3D to_intel_crtc(crtc_state->uapi.crtc); >- struct drm_i915_private *i915 =3D to_i915(crtc->base.dev); >+ struct intel_display *display =3D to_intel_display(crtc_state); >=20 >- if (DISPLAY_VER(i915) < 12) >+ if (DISPLAY_VER(display) < 12) > return 0; >=20 > return DIV_ROUND_UP_ULL(mul_u32_u32(intel_bw_crtc_data_rate(crtc_= state), 10), 512); >@@ -849,13 +854,14 @@ static unsigned int intel_bw_num_active_planes(struc= t drm_i915_private *dev_priv > static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv, > const struct intel_bw_state *bw_st= ate) > { >+ struct intel_display *display =3D &dev_priv->display; > unsigned int data_rate =3D 0; > enum pipe pipe; >=20 > for_each_pipe(dev_priv, pipe) > data_rate +=3D bw_state->data_rate[pipe]; >=20 >- if (DISPLAY_VER(dev_priv) >=3D 13 && i915_vtd_active(dev_priv)) >+ if (DISPLAY_VER(display) >=3D 13 && i915_vtd_active(dev_priv)) > data_rate =3D DIV_ROUND_UP(data_rate * 105, 100); >=20 > return data_rate; >@@ -1137,13 +1143,14 @@ static int intel_bw_check_qgv_points(struct drm_i9= 15_private *i915, > const struct intel_bw_state *old_bw_= state, > struct intel_bw_state *new_bw_state) > { >+ struct intel_display *display =3D &i915->display; > unsigned int data_rate =3D intel_bw_data_rate(i915, new_bw_state)= ; > unsigned int num_active_planes =3D > intel_bw_num_active_planes(i915, new_bw_state); >=20 > data_rate =3D DIV_ROUND_UP(data_rate, 1000); >=20 >- if (DISPLAY_VER(i915) >=3D 14) >+ if (DISPLAY_VER(display) >=3D 14) > return mtl_find_qgv_points(i915, data_rate, num_active_pl= anes, > new_bw_state); > else >@@ -1201,8 +1208,8 @@ static void skl_plane_calc_dbuf_bw(struct intel_bw_s= tate *bw_state, > static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state, > const struct intel_crtc_state *crtc_sta= te) > { >+ struct intel_display *display =3D to_intel_display(crtc_state); > struct intel_crtc *crtc =3D to_intel_crtc(crtc_state->uapi.crtc); >- struct drm_i915_private *i915 =3D to_i915(crtc->base.dev); > struct intel_dbuf_bw *crtc_bw =3D &bw_state->dbuf_bw[crtc->pipe]; > enum plane_id plane_id; >=20 >@@ -1223,7 +1230,7 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_st= ate *bw_state, > &crtc_state->wm.skl.plane_ddb[plan= e_id], > crtc_state->data_rate[plane_id]); >=20 >- if (DISPLAY_VER(i915) < 11) >+ if (DISPLAY_VER(display) < 11) > skl_plane_calc_dbuf_bw(bw_state, crtc, plane_id, > &crtc_state->wm.skl.plane_= ddb_y[plane_id], > crtc_state->data_rate[plan= e_id]); >@@ -1278,6 +1285,7 @@ int intel_bw_min_cdclk(struct drm_i915_private *i915= , > int intel_bw_calc_min_cdclk(struct intel_atomic_state *state, > bool *need_cdclk_calc) > { >+ struct intel_display *display =3D to_intel_display(state); > struct drm_i915_private *dev_priv =3D to_i915(state->base.dev); > struct intel_bw_state *new_bw_state =3D NULL; > const struct intel_bw_state *old_bw_state =3D NULL; >@@ -1287,7 +1295,7 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_stat= e *state, > struct intel_crtc *crtc; > int i; >=20 >- if (DISPLAY_VER(dev_priv) < 9) >+ if (DISPLAY_VER(display) < 9) > return 0; >=20 > for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { >@@ -1397,6 +1405,7 @@ static int intel_bw_check_data_rate(struct intel_ato= mic_state *state, bool *chan >=20 > int intel_bw_atomic_check(struct intel_atomic_state *state) > { >+ struct intel_display *display =3D to_intel_display(state); > bool changed =3D false; > struct drm_i915_private *i915 =3D to_i915(state->base.dev); > struct intel_bw_state *new_bw_state; >@@ -1404,7 +1413,7 @@ int intel_bw_atomic_check(struct intel_atomic_state = *state) > int ret; >=20 > /* FIXME earlier gens need some checks too */ >- if (DISPLAY_VER(i915) < 11) >+ if (DISPLAY_VER(display) < 11) > return 0; >=20 > ret =3D intel_bw_check_data_rate(state, &changed); >@@ -1475,7 +1484,7 @@ int intel_bw_init(struct drm_i915_private *i915) > * Limit this only if we have SAGV. And for Display version 14 on= wards > * sagv is handled though pmdemand requests > */ >- if (intel_has_sagv(i915) && IS_DISPLAY_VER(i915, 11, 13)) >+ if (intel_has_sagv(i915) && IS_DISPLAY_VER(display, 11, 13)) > icl_force_disable_sagv(i915, state); >=20 > return 0; >--=20 >2.48.1 >