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From: Gustavo Sousa <gustavo.sousa@intel.com>
To: Aradhya Bhatia <aradhya.bhatia@intel.com>,
	Matt Roper <matthew.d.roper@intel.com>
Cc: Intel XE List <intel-xe@lists.freedesktop.org>,
	Tejas Upadhyay <tejas.upadhyay@intel.com>,
	Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>,
	Aradhya Bhatia <aradhya.bhatia@intel.com>
Subject: Re: [PATCH v2] drm/xe/xe2hpg: Add Wa_22021007897
Date: Wed, 7 May 2025 11:04:32 -0300	[thread overview]
Message-ID: <174662667213.2473.4222988895493880968@intel.com> (raw)
In-Reply-To: <20250507101112.4678-1-aradhya.bhatia@intel.com>

Quoting Aradhya Bhatia (2025-05-07 07:11:12-03:00)
>Add Wa_22021007897 for the Xe2_HPG (graphics version: 20.01) platform.

s/platform/IP/

>It is a permanent workaround, and applicable on all the steppings.
>
>Signed-off-by: Aradhya Bhatia <aradhya.bhatia@intel.com>

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>

>---
>Changes in v2:
>  - Fix typo in the SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE macro.
>
> drivers/gpu/drm/xe/regs/xe_gt_regs.h | 1 +
> drivers/gpu/drm/xe/xe_wa.c           | 4 ++++
> 2 files changed, 5 insertions(+)
>
>diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>index cbb9f7cbcfc0..5cd5ab8529c5 100644
>--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>@@ -156,6 +156,7 @@
> #define XEHPG_SC_INSTDONE_EXTRA2                XE_REG_MCR(0x7108)
> 
> #define COMMON_SLICE_CHICKEN4                        XE_REG(0x7300, XE_REG_OPTION_MASKED)
>+#define   SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE        REG_BIT(12)
> #define   DISABLE_TDC_LOAD_BALANCING_CALC        REG_BIT(6)
> 
> #define COMMON_SLICE_CHICKEN3                                XE_REG(0x7304, XE_REG_OPTION_MASKED)
>diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
>index 6f6563cc7430..67196baa4249 100644
>--- a/drivers/gpu/drm/xe/xe_wa.c
>+++ b/drivers/gpu/drm/xe/xe_wa.c
>@@ -827,6 +827,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>           XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
>           XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_CLIP_NEGATIVE_BOUNDING_BOX))
>         },
>+        { XE_RTP_NAME("22021007897"),
>+          XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
>+          XE_RTP_ACTIONS(SET(COMMON_SLICE_CHICKEN4, SBE_PUSH_CONSTANT_BEHIND_FIX_ENABLE))
>+        },
> 
>         /* Xe3_LPG */
>         { XE_RTP_NAME("14021490052"),
>
>base-commit: a127cd437da1f18b6ecc9e03226d8e2b2aa79dab
>-- 
>2.43.0
>

  parent reply	other threads:[~2025-05-07 14:04 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-07 10:11 [PATCH v2] drm/xe/xe2hpg: Add Wa_22021007897 Aradhya Bhatia
2025-05-07 10:16 ` ✓ CI.Patch_applied: success for drm/xe/xe2hpg: Add Wa_22021007897 (rev2) Patchwork
2025-05-07 10:16 ` ✓ CI.checkpatch: " Patchwork
2025-05-07 10:18 ` ✓ CI.KUnit: " Patchwork
2025-05-07 10:26 ` ✓ CI.Build: " Patchwork
2025-05-07 10:28 ` ✓ CI.Hooks: " Patchwork
2025-05-07 10:30 ` ✓ CI.checksparse: " Patchwork
2025-05-07 10:56 ` ✓ Xe.CI.BAT: " Patchwork
2025-05-07 12:36 ` ✗ Xe.CI.Full: failure " Patchwork
2025-05-09  5:59   ` Aradhya Bhatia
2025-05-07 14:04 ` Gustavo Sousa [this message]
2025-05-08 13:55 ` [PATCH v2] drm/xe/xe2hpg: Add Wa_22021007897 Upadhyay, Tejas
2025-05-08 15:54   ` Matt Roper
2025-05-09  5:22     ` Upadhyay, Tejas

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