From: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>
To: Suraj Kandpal <suraj.kandpal@intel.com>,
<intel-xe@lists.freedesktop.org>,
<intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH v2 1/3] drm/i915/ddi: add helper to compute DDI clock frequency
Date: Wed, 12 Aug 2026 09:13:11 +0530 [thread overview]
Message-ID: <174d672b-b63a-4ff6-894e-204100fe351b@intel.com> (raw)
In-Reply-To: <20260811175844.2613721-2-suraj.kandpal@intel.com>
On 8/11/2026 11:28 PM, Suraj Kandpal wrote:
> Add intel_ddi_link_symbol_clock() to return the DDI clock frequency for
> a given port clock:
> DP 8b/10b : rate
> DP 128b/132b (UHBR) : (10 / 32) * rate
> HDMI FRL : (10 / 18) * rate
> HDMI TMDS : rate
>
> The DP case reuses intel_dp_link_symbol_clock().
> This will help in upcoming commits to decide value to be written
> in DDI_CLK_VALFREQ.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> v1 -> v2
> -Update commit message with correct formula (Jani)
>
> drivers/gpu/drm/i915/display/intel_ddi.c | 11 +++++++++++
> drivers/gpu/drm/i915/display/intel_ddi.h | 1 +
> 2 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index bf5788c5bbd3..dd9064592ec9 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -1529,6 +1529,17 @@ int intel_ddi_level(struct intel_encoder *encoder,
> return level;
> }
>
> +int intel_ddi_link_symbol_clock(struct intel_encoder *encoder, int clock)
> +{
> + if (intel_encoder_is_dp(encoder))
> + return intel_dp_link_symbol_clock(clock);
> +
> + if (intel_hdmi_is_frl(clock))
> + return DIV_ROUND_CLOSEST(clock * 10, 18);
> +
> + return clock;
> +}
> +
> static void
> hsw_set_signal_levels(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
> index 580ecb09b8b6..239d5a403f91 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.h
> @@ -81,6 +81,7 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
> int intel_ddi_level(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> int lane);
> +int intel_ddi_link_symbol_clock(struct intel_encoder *encoder, int clock);
> void intel_ddi_update_active_dpll(struct intel_atomic_state *state,
> struct intel_encoder *encoder,
> struct intel_crtc *crtc);
next prev parent reply other threads:[~2026-08-12 3:43 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-11 17:58 [PATCH v2 0/3] Fix value being written to DDI_CLK_VALFREQ Suraj Kandpal
2026-08-11 17:58 ` [PATCH v2 1/3] drm/i915/ddi: add helper to compute DDI clock frequency Suraj Kandpal
2026-08-12 3:43 ` Nautiyal, Ankit K [this message]
2026-08-11 17:58 ` [PATCH v2 2/3] drm/i915/cx0: program DDI_CLK_VALFREQ with " Suraj Kandpal
2026-08-12 3:49 ` Nautiyal, Ankit K
2026-08-12 4:24 ` Kandpal, Suraj
2026-08-12 9:03 ` Jani Nikula
2026-08-12 9:11 ` Kandpal, Suraj
2026-08-11 17:58 ` [PATCH v2 3/3] drm/i915/lt_phy: " Suraj Kandpal
2026-08-12 3:50 ` Nautiyal, Ankit K
2026-08-11 18:05 ` ✓ CI.KUnit: success for Fix value being written to DDI_CLK_VALFREQ (rev2) Patchwork
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