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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) by PH0PR11MB7472.namprd11.prod.outlook.com (2603:10b6:510:28c::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8901.37; Fri, 18 Jul 2025 12:58:45 +0000 Received: from PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350]) by PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350%4]) with mapi id 15.20.8835.026; Fri, 18 Jul 2025 12:58:45 +0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In-Reply-To: References: <20250717063259.440086-1-jouni.hogander@intel.com> <175275909975.1809.8747168482147911326@intel.com> Subject: Re: [PATCH] drm/i915/display: Write PHY_CMN1_CONTROL only when using AUXLess ALPM From: Gustavo Sousa To: "Hogander, Jouni" , "intel-gfx@lists.freedesktop.org" , "intel-xe@lists.freedesktop.org" Date: Fri, 18 Jul 2025 09:58:36 -0300 Message-ID: <175284351608.1809.17923503412794799848@intel.com> User-Agent: alot/0.12.dev27+gd21c920b07eb X-ClientProxiedBy: MW4PR03CA0064.namprd03.prod.outlook.com (2603:10b6:303:b6::9) To PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8287:EE_|PH0PR11MB7472:EE_ X-MS-Office365-Filtering-Correlation-Id: e4e39d71-3580-4957-f17e-08ddc5fad444 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014; 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According to Bspec >> > > Configuring >> > > LFPS sending is needed only when using AUXLess ALPM. This patch >> > > avoids >> > > these failures by configuring LFPS sending only when using >> > > AUXLess >> > > ALPM. >> >=20 >> > Hm... But then with this patch we are missing writing zero to that >> > bit >> > when necessary, no? >>=20 >> That shouldn't be necessary as 0 is the reset value. >>=20 >> >=20 >> > Could the timeouts be happening because intel_cx0_rmw() is getting >> > called without calling >> > intel_cx0_phy_transaction_begin()/intel_cx0_phy_transaction_end()? >>=20 >> I wasn't aware about these. I will try them. > >I tested this and it doesn't help: Okay. Well, I still find it weird that this would time out for one case and not time out for another... Do we have confirmation that this is working fine for the AUX-Less ALPM case? I wonder if we should rather do this step together with intel_c10_pll_program(). Note that, for C10, there is also a required step to set PHY_C10_VDR_CONTROL1[2] before accessing the msgbus. > >diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c >b/drivers/gpu/drm/i915/display/intel_cx0_phy.c >index ed8e640b96b0..e6ff7f07b2e3 100644 >--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c >+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c >@@ -3239,6 +3239,7 @@ void intel_lnl_mac_transmit_lfps(struct >intel_encoder *encoder, > const struct intel_crtc_state >*crtc_state) > { > struct intel_display *display =3D to_intel_display(encoder); >+ intel_wakeref_t wakeref; > u8 owned_lane_mask =3D intel_cx0_get_owned_lane_mask(encoder); > bool enable =3D >intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder), > crtc_state); >@@ -3247,6 +3248,8 @@ void intel_lnl_mac_transmit_lfps(struct >intel_encoder *encoder, > if (DISPLAY_VER(display) < 20) > return; >=20 >+ wakeref =3D intel_cx0_phy_transaction_begin(encoder); >+ > for (i =3D 0; i < 4; i++) { > int tx =3D i % 2 + 1; > u8 lane_mask =3D i < 2 ? INTEL_CX0_LANE0 : >INTEL_CX0_LANE1; >@@ -3259,6 +3262,8 @@ void intel_lnl_mac_transmit_lfps(struct >intel_encoder *encoder, > enable ? CONTROL0_MAC_TRANSMIT_LFPS : 0, > MB_WRITE_COMMITTED); > } >+ >+ intel_cx0_phy_transaction_end(encoder, wakeref); > } > >Do you think I should still add this change as well? If we are still going with this function instead of doing it in intel_c10_pll_program(), then yes. -- Gustavo Sousa > >>=20 >> BR, >>=20 >> Jouni H=C3=B6gander >>=20 >> >=20 >> > >=20 >> > > Fixes: 9dc619680de4 ("drm/i915/display: Add function to configure >> > > LFPS sending") >> > > Signed-off-by: Jouni H=C3=B6gander >> > > --- >> > > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 +++++------ >> > > 1 file changed, 5 insertions(+), 6 deletions(-) >> > >=20 >> > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c >> > > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c >> > > index ed8e640b96b0..9cfc3187aeab 100644 >> > > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c >> > > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c >> > > @@ -3239,14 +3239,14 @@ void intel_lnl_mac_transmit_lfps(struct >> > > intel_encoder *encoder, >> > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 const struct intel_crtc= _state >> > > *crtc_state) >> > > { >> > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 struct intel_display *dis= play =3D >> > > to_intel_display(encoder); >> > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 u8 owned_lane_mask =3D >> > > intel_cx0_get_owned_lane_mask(encoder); >> > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 bool enable =3D >> > > intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder), >> > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 crtc_state); >> > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 u8 owned_lane_mask; >> > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 int i; >> > >=20 >> > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (DISPLAY_VER(display)= < 20) >> > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (DISPLAY_VER(display)= < 20 || >> > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 >> > > !intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder), >> > > crtc_state)) >> > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 return; >> > >=20 >> > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 owned_lane_mask =3D >> > > intel_cx0_get_owned_lane_mask(encoder); >> >=20 >> > This optimization could be on it's own patch. > >Ok, maybe I leave that out or add own patch. > >BR, > >Jouni H=C3=B6gander > > >> >=20 >> > -- >> > Gustavo Sousa >> >=20 >> > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 for (i =3D 0; i < 4; i++)= { >> > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 int tx =3D i % 2 + 1; >> > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 u8 lane_mask =3D i < 2 ? INTEL_CX0_LANE0 : >> > > INTEL_CX0_LANE1; >> > > @@ -3256,8 +3256,7 @@ void intel_lnl_mac_transmit_lfps(struct >> > > intel_encoder *encoder, >> > >=20 >> > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 intel_cx0_rmw(encoder, lane_mask, >> > > PHY_CMN1_CONTROL(tx, 0), >> > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CONTROL0_MAC_TRANSMIT_LFPS, >> > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 enable ? >> > > CONTROL0_MAC_TRANSMIT_LFPS >> > > : 0, >> > > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 MB_WRITE_COMMITTED); >> > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CONTROL0_MAC_TRANSMIT_LFPS, >> > > MB_WRITE_COMMITTED); >> > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } >> > > } >> > >=20 >> > > --=20 >> > > 2.43.0 >> > >=20 >>=20 >