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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) by SJ0PR11MB4944.namprd11.prod.outlook.com (2603:10b6:a03:2ae::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8922.39; Fri, 18 Jul 2025 16:33:35 +0000 Received: from PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350]) by PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350%4]) with mapi id 15.20.8835.026; Fri, 18 Jul 2025 16:33:35 +0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In-Reply-To: References: <20250717051603.1036746-1-chaitanya.kumar.borah@intel.com> <175275376596.1809.4970039481532019393@intel.com> Subject: Re: [PATCH] drm/i915/display: Skip unavailable power wells based on pipe mask From: Gustavo Sousa CC: , , , To: Chaitanya Kumar Borah , Imre Deak Date: Fri, 18 Jul 2025 13:33:26 -0300 Message-ID: <175285640686.1809.2888738151042642518@intel.com> User-Agent: alot/0.12.dev27+gd21c920b07eb X-ClientProxiedBy: MW4PR03CA0100.namprd03.prod.outlook.com (2603:10b6:303:b7::15) To PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8287:EE_|SJ0PR11MB4944:EE_ X-MS-Office365-Filtering-Correlation-Id: 98ba28ed-b53b-4e38-94b6-08ddc618d74c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014; 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Add a che= ck >> >to ensure we only allocate and initialize power wells whose associated >> >pipes are available on the platform. >> > >> >This avoids unnecessary mapping of power wells, particularly when platf= orms >> >support a subset of pipes described in the power well descriptors. >> > >> >Suggested-by: Imre Deak >> >Signed-off-by: Chaitanya Kumar Borah >> >--- >> > .../i915/display/intel_display_power_map.c | 19 +++++++++++++++++-- >> > 1 file changed, 17 insertions(+), 2 deletions(-) >> > >> >diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/d= rivers/gpu/drm/i915/display/intel_display_power_map.c >> >index 77268802b55e..ca73e4084354 100644 >> >--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c >> >+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c >> >@@ -1748,6 +1748,16 @@ static void init_power_well_domains(const struct= i915_power_well_instance *inst, >> > for_each_power_well_instance_in_desc_list((_descs)->li= st, (_descs)->count, \ >> > (_desc), (_i= nst)) >> >=20 >> >+static bool >> >+is_power_well_available(struct intel_display *display, const struct i9= 15_power_well_desc *desc) >> >+{ >> >+ if (desc->irq_pipe_mask && >> >+ !(desc->irq_pipe_mask & DISPLAY_RUNTIME_INFO(display)->pip= e_mask)) >>=20 >> According to irq_pipe_mask's documentation, that member contains a "mask >> of pipes whose IRQ logic is backed by the pw". I think we are >> overloading the meaning of that field with this logic. >>=20 >> * Do we have guarantees that irq_pipe_mask will always be associated >> with the power well that powers the pipe? > >It is the case on all the platforms and so it also provides the required >way to identify the power well for a particular pipe. irq_pipe_mask >could be renamed to pipe_mask accordingly. I mean, that *exclusively* powers the pipe(s). As an example, bdw_pwdoms_display appears to be responsible not only for pipe B and C, but also ddi lanes and audio, for example. > >> * If the power well that has irq_pipe_mask is also used to power >> something else than the pipes, we could have issues if pipes in that >> mask are fused off. >> >> I'm leaning more toward a solution that makes POWER_DOMAIN_INIT map to >> POWER_DOMAIN_PIPE_* based on DISPLAY_RUNTIME_INFO(display)->pipe_mask. I >> have some idea of how to do that without rewriting code to use a >> hierarchical structure (which IMO would be ideal, but takes more >> effort). >>=20 >> The idea is to, during runtime and initialization of the mapping, set >> the bit respective to POWER_DOMAIN_INIT in each power well that has the >> bit for POWER_DOMAIN_PIPE_* set for non-fused off pipes. That would >> also require removing the POWER_DOMAIN_INIT from the static mapping for >> power wells directly responsible for POWER_DOMAIN_PIPE_*. > >Power wells that don't exist on a platform shouldn't be registered in >the first place, so it's not enough to only remove them from the power >well->domain mapping, while still registering the power well. Otherwise >these non-existant power wells would still be accessed while disabling >any unused power well during driver loading/resume. Also these power >wells non-existant on a platform would be incorrectly listed in debugfs >and other state dumps. > >However, I realized that pipe power wells that do exist on a platform, >but for which the corresponing pipe is fused off (for instance pipe >A/B/C on WCL) we still need to register the power well. On some >platforms at least such power wells may be enabled after HW reset/by >BIOS and so these still need to be checked and disabled if needed during >driver loading/resume. I.e. instead of the above Ah, I see. Yeah, that makes sense. Thanks for the details! Well, although Bspec overview page tells that WCL's display has only pipes A, B and C, the page specific for power wells still lists power well D. So I'm wondering if WCL display just has pipe D fused off and the power well still exists or if power well D being listed in Bspec is just a documentation mistake. I'll check with the hardware team. > >DISPLAY_RUNTIME_INFO(display)->pipe_mask > >something like the following should be used: > >u8 pipe_pw_mask(display) >{ > if (DISPLAY_VERx100(display) =3D=3D 3002) > return BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); > > return BIT(I915_MAX_PIPES + 1) - 1; >} Well, if power well D does not exist indeed (i.e. not a case of pipe D fused-off), we need either this above or maybe go back to Chaitanya's original patch. I think I prefer the original patch, making the power well mapping explicit. -- Gustavo Sousa > >> -- >> Gustavo Sousa >>=20 >> >+ return false; >> >+ >> >+ return true; >> >+} >> >+ >> > static int >> > __set_power_wells(struct i915_power_domains *power_domains, >> > const struct i915_power_well_desc_list *power_well_d= escs, >> >@@ -1763,8 +1773,10 @@ __set_power_wells(struct i915_power_domains *pow= er_domains, >> > int power_well_count =3D 0; >> > int plt_idx =3D 0; >> >=20 >> >- for_each_power_well_instance(power_well_descs, power_well_desc= s_sz, desc_list, desc, inst) >> >- power_well_count++; >> >+ for_each_power_well_instance(power_well_descs, power_well_desc= s_sz, desc_list, desc, inst) { >> >+ if (is_power_well_available(display, desc)) >> >+ power_well_count++; >> >+ } >> >=20 >> > power_domains->power_well_count =3D power_well_count; >> > power_domains->power_wells =3D >> >@@ -1778,6 +1790,9 @@ __set_power_wells(struct i915_power_domains *powe= r_domains, >> > struct i915_power_well *pw =3D &power_domains->power_w= ells[plt_idx]; >> > enum i915_power_well_id id =3D inst->id; >> >=20 >> >+ if (!is_power_well_available(display, desc)) >> >+ continue; >> >+ >> > pw->desc =3D desc; >> > drm_WARN_ON(display->drm, >> > overflows_type(inst - desc->instances->lis= t, pw->instance_idx)); >> >--=20 >> >2.25.1 >> >