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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) by DS4PPFCAADA7A6C.namprd11.prod.outlook.com (2603:10b6:f:fc02::4d) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9182.20; Wed, 8 Oct 2025 13:28:11 +0000 Received: from PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350]) by PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350%7]) with mapi id 15.20.9182.017; Wed, 8 Oct 2025 13:28:11 +0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In-Reply-To: <20251007204829.1468209-29-matthew.d.roper@intel.com> References: <20251007204829.1468209-25-matthew.d.roper@intel.com> <20251007204829.1468209-29-matthew.d.roper@intel.com> Subject: Re: [PATCH v4 04/23] drm/xe: Move 'vm_max_level' flag back to platform descriptor From: Gustavo Sousa CC: , Lucas De Marchi To: Matt Roper , Date: Wed, 8 Oct 2025 10:28:08 -0300 Message-ID: <175993008801.201562.9741607596597062253@intel.com> User-Agent: alot/0.12.dev22+g972188619 X-ClientProxiedBy: BYAPR04CA0002.namprd04.prod.outlook.com (2603:10b6:a03:40::15) To PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8287:EE_|DS4PPFCAADA7A6C:EE_ X-MS-Office365-Filtering-Correlation-Id: 29aca499-084a-43b5-7384-08de066e86b6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|1800799024; 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This is also a trait that should be tied to the platform even >if the graphics IP itself is not present (e.g., if we disable the >primary GT via configfs). > >v2: > - Drop default value of 4 and explicitly set the value in each platform > descriptor. (Lucas) >v3: > - Drop outdated code comment and commit message paragraph about default > value. (Gustavo) > >Cc: Lucas De Marchi >Cc: Gustavo Sousa >Signed-off-by: Matt Roper >--- > drivers/gpu/drm/xe/xe_pci.c | 22 ++++++++++++++-------- > drivers/gpu/drm/xe/xe_pci_types.h | 2 +- > 2 files changed, 15 insertions(+), 9 deletions(-) > >diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c >index 69ed987fef67..8688f40f55d8 100644 >--- a/drivers/gpu/drm/xe/xe_pci.c >+++ b/drivers/gpu/drm/xe/xe_pci.c >@@ -51,13 +51,10 @@ __diag_ignore_all("-Woverride-init", "Allow field over= rides in table"); >=20 > static const struct xe_graphics_desc graphics_xelp =3D { > .hw_engine_mask =3D BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS= 0), >- >- .vm_max_level =3D 3, > }; >=20 > #define XE_HP_FEATURES \ >- .has_range_tlb_inval =3D true, \ >- .vm_max_level =3D 3 >+ .has_range_tlb_inval =3D true >=20 > static const struct xe_graphics_desc graphics_xehpg =3D { > .hw_engine_mask =3D >@@ -82,7 +79,6 @@ static const struct xe_graphics_desc graphics_xehpc =3D = { > BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3), >=20 > XE_HP_FEATURES, >- .vm_max_level =3D 4, > .vram_flags =3D XE_VRAM_FLAGS_NEED64K, >=20 > .has_asid =3D 1, >@@ -105,7 +101,6 @@ static const struct xe_graphics_desc graphics_xelpg = =3D { > .has_range_tlb_inval =3D 1, \ > .has_usm =3D 1, \ > .has_64bit_timestamp =3D 1, \ >- .vm_max_level =3D 4, \ > .hw_engine_mask =3D \ > BIT(XE_HW_ENGINE_RCS0) | \ > BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \ >@@ -183,6 +178,7 @@ static const struct xe_device_desc rkl_desc =3D { > .max_gt_per_tile =3D 1, > .require_force_probe =3D true, > .va_bits =3D 48, >+ .vm_max_level =3D 3, > }; I think we are missing setting ".vm_max_level =3D 3" for tgl_desc as well. With that fixed, Reviewed-by: Gustavo Sousa >=20 > static const u16 adls_rpls_ids[] =3D { INTEL_RPLS_IDS(NOP), 0 }; >@@ -202,6 +198,7 @@ static const struct xe_device_desc adl_s_desc =3D { > {}, > }, > .va_bits =3D 48, >+ .vm_max_level =3D 3, > }; >=20 > static const u16 adlp_rplu_ids[] =3D { INTEL_RPLU_IDS(NOP), 0 }; >@@ -221,6 +218,7 @@ static const struct xe_device_desc adl_p_desc =3D { > {}, > }, > .va_bits =3D 48, >+ .vm_max_level =3D 3, > }; >=20 > static const struct xe_device_desc adl_n_desc =3D { >@@ -234,6 +232,7 @@ static const struct xe_device_desc adl_n_desc =3D { > .max_gt_per_tile =3D 1, > .require_force_probe =3D true, > .va_bits =3D 48, >+ .vm_max_level =3D 3, > }; >=20 > #define DGFX_FEATURES \ >@@ -251,6 +250,7 @@ static const struct xe_device_desc dg1_desc =3D { > .max_gt_per_tile =3D 1, > .require_force_probe =3D true, > .va_bits =3D 48, >+ .vm_max_level =3D 3, > }; >=20 > static const u16 dg2_g10_ids[] =3D { INTEL_DG2_G10_IDS(NOP), INTEL_ATS_M1= 50_IDS(NOP), 0 }; >@@ -268,7 +268,8 @@ static const u16 dg2_g12_ids[] =3D { INTEL_DG2_G12_IDS= (NOP), 0 }; > { XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \ > { } \ > }, \ >- .va_bits =3D 48 >+ .va_bits =3D 48, \ >+ .vm_max_level =3D 3 >=20 > static const struct xe_device_desc ats_m_desc =3D { > .pre_gmdid_graphics_ip =3D &graphics_ip_xehpg, >@@ -307,6 +308,7 @@ static const __maybe_unused struct xe_device_desc pvc_= desc =3D { > .max_remote_tiles =3D 1, > .require_force_probe =3D true, > .va_bits =3D 57, >+ .vm_max_level =3D 4, > .has_mbx_power_limits =3D false, > }; >=20 >@@ -319,6 +321,7 @@ static const struct xe_device_desc mtl_desc =3D { > .has_pxp =3D true, > .max_gt_per_tile =3D 2, > .va_bits =3D 48, >+ .vm_max_level =3D 4, > }; >=20 > static const struct xe_device_desc lnl_desc =3D { >@@ -329,6 +332,7 @@ static const struct xe_device_desc lnl_desc =3D { > .max_gt_per_tile =3D 2, > .needs_scratch =3D true, > .va_bits =3D 48, >+ .vm_max_level =3D 4, > }; >=20 > static const struct xe_device_desc bmg_desc =3D { >@@ -345,6 +349,7 @@ static const struct xe_device_desc bmg_desc =3D { > .max_gt_per_tile =3D 2, > .needs_scratch =3D true, > .va_bits =3D 48, >+ .vm_max_level =3D 4, > }; >=20 > static const struct xe_device_desc ptl_desc =3D { >@@ -355,6 +360,7 @@ static const struct xe_device_desc ptl_desc =3D { > .max_gt_per_tile =3D 2, > .needs_scratch =3D true, > .va_bits =3D 48, >+ .vm_max_level =3D 4, > }; >=20 > #undef PLATFORM >@@ -593,6 +599,7 @@ static int xe_info_init_early(struct xe_device *xe, >=20 > xe->info.dma_mask_size =3D desc->dma_mask_size; > xe->info.va_bits =3D desc->va_bits; >+ xe->info.vm_max_level =3D desc->vm_max_level; >=20 > xe->info.is_dgfx =3D desc->is_dgfx; > xe->info.has_fan_control =3D desc->has_fan_control; >@@ -723,7 +730,6 @@ static int xe_info_init(struct xe_device *xe, > } >=20 > xe->info.vram_flags =3D graphics_desc->vram_flags; >- xe->info.vm_max_level =3D graphics_desc->vm_max_level; > xe->info.has_asid =3D graphics_desc->has_asid; > xe->info.has_atomic_enable_pte_bit =3D graphics_desc->has_atomic_= enable_pte_bit; > if (xe->info.platform !=3D XE_PVC) >diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci= _types.h >index 796439571abe..6354280584d9 100644 >--- a/drivers/gpu/drm/xe/xe_pci_types.h >+++ b/drivers/gpu/drm/xe/xe_pci_types.h >@@ -31,6 +31,7 @@ struct xe_device_desc { > u8 max_remote_tiles:2; > u8 max_gt_per_tile:2; > u8 va_bits; >+ u8 vm_max_level; >=20 > u8 require_force_probe:1; > u8 is_dgfx:1; >@@ -52,7 +53,6 @@ struct xe_device_desc { > }; >=20 > struct xe_graphics_desc { >- u8 vm_max_level; > u8 vram_flags; >=20 > u64 hw_engine_mask; /* hardware engines provided by graphi= cs IP */ >--=20 >2.51.0 >