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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) by CO1PR11MB4851.namprd11.prod.outlook.com (2603:10b6:303:9b::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9182.16; Wed, 8 Oct 2025 14:06:19 +0000 Received: from PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350]) by PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350%7]) with mapi id 15.20.9182.017; Wed, 8 Oct 2025 14:06:18 +0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In-Reply-To: <20251007204829.1468209-47-matthew.d.roper@intel.com> References: <20251007204829.1468209-25-matthew.d.roper@intel.com> <20251007204829.1468209-47-matthew.d.roper@intel.com> Subject: Re: [PATCH v4 22/23] drm/xe/configfs: Add attribute to disable GT types From: Gustavo Sousa CC: To: Matt Roper , Date: Wed, 8 Oct 2025 11:06:14 -0300 Message-ID: <175993237464.201562.8329727487094559284@intel.com> User-Agent: alot/0.12.dev22+g972188619 X-ClientProxiedBy: SJ0PR05CA0059.namprd05.prod.outlook.com (2603:10b6:a03:33f::34) To PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8287:EE_|CO1PR11MB4851:EE_ X-MS-Office365-Filtering-Correlation-Id: 8c20bb28-9ebf-456b-facc-08de0673d9fa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014; 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Add a configfs >attribute to allow this kind of control for debugging. > >With today's platforms and software design, this configuration setting >is only effective for disabling the media GT since the driver currently >requires that there always be a primary GT to probe the device. However >this might change in the future --- in theory it should be possible >(with some additional driver work) to allow an igpu device to come up >with only the media GT and no primary GT. Or to allow an igpu device to >come up with no GTs at all (for display-only usage). A primary GT will >likely always be required on dgpu platforms because we rely on the BCS >engines inside the primary GT for various vram operations. > >v2: > - Expand/clarify kerneldoc for configfs attribute. (Gustavo) > - Tighten type usage in gt_types[] structure. (Gustavo) > - Adjust string parsing/name matching to match exact GT names and not > accept partial names. (Gustavo) > >v3: > - Switch to scope-based cleanup in gt_types_allowed_store() to fix a > leak if the device is already bound. (Gustavo) > - Switch configfs lookup interface to two boolean functions that > specify whether primary/media are supported rather than one function > that returns a mask. This is simpler to use and understand. > >Cc: Gustavo Sousa >Signed-off-by: Matt Roper >--- > drivers/gpu/drm/xe/xe_configfs.c | 145 +++++++++++++++++++++++++++++++ > drivers/gpu/drm/xe/xe_configfs.h | 4 + > drivers/gpu/drm/xe/xe_pci.c | 22 +++++ > 3 files changed, 171 insertions(+) > >diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_conf= igfs.c >index 139663423185..e36cc5e1bc8f 100644 >--- a/drivers/gpu/drm/xe/xe_configfs.c >+++ b/drivers/gpu/drm/xe/xe_configfs.c >@@ -15,6 +15,7 @@ >=20 > #include "instructions/xe_mi_commands.h" > #include "xe_configfs.h" >+#include "xe_gt_types.h" > #include "xe_hw_engine_types.h" > #include "xe_module.h" > #include "xe_pci_types.h" >@@ -56,6 +57,7 @@ > * : > * =E2=94=94=E2=94=80=E2=94=80 0000:03:00.0 > * =E2=94=9C=E2=94=80=E2=94=80 survivability_mode >+ * =E2=94=9C=E2=94=80=E2=94=80 gt_types_allowed > * =E2=94=9C=E2=94=80=E2=94=80 engines_allowed > * =E2=94=94=E2=94=80=E2=94=80 enable_psmi > * >@@ -79,6 +81,44 @@ > * > * This attribute can only be set before binding to the device. > * >+ * Allowed GT types: >+ * ----------------- >+ * >+ * Allow only specific types of GTs to be detected and initialized by the >+ * driver. Any combination of GT types can be enabled/disabled, although >+ * some settings will cause the device to fail to probe. >+ * >+ * Writes support both comma- and newline-separated input format. Reads >+ * will always return one GT type per line. "primary" and "media" are the >+ * GT type names supported by this interface. >+ * >+ * This attribute can only be set before binding to the device. >+ * >+ * Examples: >+ * >+ * Allow both primary and media GTs to be initialized and used. This mat= ches >+ * the driver's default behavior:: >+ * >+ * # echo 'primary,media' > /sys/kernel/config/xe/0000:03:00.0/gt_= types_allowed >+ * >+ * Allow only the primary GT of each tile to be initialized and used, >+ * effectively disabling the media GT if it exists on the platform:: >+ * >+ * # echo 'primary' > /sys/kernel/config/xe/0000:03:00.0/gt_types_= allowed >+ * >+ * Allow only the media GT of each tile to be initialized and used, >+ * effectively disabling the primary GT. **This configuration will cause >+ * device probe failure on all current platforms, but may be allowed on >+ * igpu platforms in the future**:: >+ * >+ * # echo 'media' > /sys/kernel/config/xe/0000:03:00.0/gt_types_al= lowed >+ * >+ * Disable all GTs. Only other GPU IP (such as display) is potentially u= sable. >+ * **This configuration will cause device probe failure on all current >+ * platforms, but may be allowed on igpu platforms in the future**:: >+ * >+ * # echo '' > /sys/kernel/config/xe/0000:03:00.0/gt_types_allowed >+ * > * Allowed engines: > * ---------------- > * >@@ -187,6 +227,7 @@ struct xe_config_group_device { > struct config_group group; >=20 > struct xe_config_device { >+ u64 gt_types_allowed; > u64 engines_allowed; > struct wa_bb ctx_restore_post_bb[XE_ENGINE_CLASS_MAX]; > struct wa_bb ctx_restore_mid_bb[XE_ENGINE_CLASS_MAX]; >@@ -201,6 +242,7 @@ struct xe_config_group_device { > }; >=20 > static const struct xe_config_device device_defaults =3D { >+ .gt_types_allowed =3D U64_MAX, > .engines_allowed =3D U64_MAX, > .survivability_mode =3D false, > .enable_psmi =3D false, >@@ -220,6 +262,7 @@ struct engine_info { > /* Some helpful macros to aid on the sizing of buffer allocation when par= sing */ > #define MAX_ENGINE_CLASS_CHARS 5 > #define MAX_ENGINE_INSTANCE_CHARS 2 >+#define MAX_GT_TYPE_CHARS 7 >=20 > static const struct engine_info engine_info[] =3D { > { .cls =3D "rcs", .mask =3D XE_HW_ENGINE_RCS_MASK, .engine_class = =3D XE_ENGINE_CLASS_RENDER }, >@@ -230,6 +273,14 @@ static const struct engine_info engine_info[] =3D { > { .cls =3D "gsccs", .mask =3D XE_HW_ENGINE_GSCCS_MASK, .engine_cl= ass =3D XE_ENGINE_CLASS_OTHER }, > }; >=20 >+static const struct { >+ const char name[MAX_GT_TYPE_CHARS + 1]; >+ enum xe_gt_type type; >+} gt_types[] =3D { >+ { .name =3D "primary", .type =3D XE_GT_TYPE_MAIN }, >+ { .name =3D "media", .type =3D XE_GT_TYPE_MEDIA }, >+}; >+ > static struct xe_config_group_device *to_xe_config_group_device(struct co= nfig_item *item) > { > return container_of(to_config_group(item), struct xe_config_group= _device, group); >@@ -292,6 +343,58 @@ static ssize_t survivability_mode_store(struct config= _item *item, const char *pa > return len; > } >=20 >+static ssize_t gt_types_allowed_show(struct config_item *item, char *page= ) >+{ >+ struct xe_config_device *dev =3D to_xe_config_device(item); >+ char *p =3D page; >+ >+ for (size_t i =3D 0; i < ARRAY_SIZE(gt_types); i++) >+ if (dev->gt_types_allowed & BIT_ULL(gt_types[i].type)) >+ p +=3D sprintf(p, "%s\n", gt_types[i].name); >+ >+ return p - page; >+} >+ >+static ssize_t gt_types_allowed_store(struct config_item *item, const cha= r *page, >+ size_t len) >+{ >+ struct xe_config_group_device *dev =3D to_xe_config_group_device(= item); >+ char *buf __free(kfree) =3D kstrdup(page, GFP_KERNEL); >+ char *p =3D buf; >+ u64 typemask =3D 0; >+ >+ if (!buf) >+ return -ENOMEM; >+ >+ while (p) { >+ char *typename =3D strsep(&p, ",\n"); >+ bool matched =3D false; >+ >+ if (typename[0] =3D=3D '\0') >+ continue; >+ >+ for (size_t i =3D 0; i < ARRAY_SIZE(gt_types); i++) { >+ if (strcmp(typename, gt_types[i].name) =3D=3D 0) = { >+ typemask |=3D BIT(gt_types[i].type); >+ matched =3D true; >+ break; >+ } >+ } >+ >+ if (!matched) >+ return -EINVAL; >+ } >+ >+ scoped_guard(mutex, &dev->lock) { >+ if (is_bound(dev)) >+ return -EBUSY; >+ >+ dev->config.gt_types_allowed =3D typemask; >+ } >+ >+ return len; >+} >+ > static ssize_t engines_allowed_show(struct config_item *item, char *page) > { > struct xe_config_device *dev =3D to_xe_config_device(item); >@@ -672,6 +775,7 @@ CONFIGFS_ATTR(, ctx_restore_mid_bb); > CONFIGFS_ATTR(, ctx_restore_post_bb); > CONFIGFS_ATTR(, enable_psmi); > CONFIGFS_ATTR(, engines_allowed); >+CONFIGFS_ATTR(, gt_types_allowed); > CONFIGFS_ATTR(, survivability_mode); >=20 > static struct configfs_attribute *xe_config_device_attrs[] =3D { >@@ -679,6 +783,7 @@ static struct configfs_attribute *xe_config_device_att= rs[] =3D { > &attr_ctx_restore_post_bb, > &attr_enable_psmi, > &attr_engines_allowed, >+ &attr_gt_types_allowed, > &attr_survivability_mode, > NULL, > }; >@@ -846,6 +951,7 @@ static void dump_custom_dev_config(struct pci_dev *pde= v, > dev->config.attr_); \ > } while (0) >=20 >+ PRI_CUSTOM_ATTR("%llx", gt_types_allowed); > PRI_CUSTOM_ATTR("%llx", engines_allowed); > PRI_CUSTOM_ATTR("%d", enable_psmi); > PRI_CUSTOM_ATTR("%d", survivability_mode); >@@ -896,6 +1002,45 @@ bool xe_configfs_get_survivability_mode(struct pci_d= ev *pdev) > return mode; > } >=20 >+static u64 get_gt_types_allowed(struct xe_device *xe) >+{ >+ struct pci_dev *pdev =3D to_pci_dev(xe->drm.dev); >+ struct xe_config_group_device *dev =3D find_xe_config_group_devic= e(pdev); >+ u64 mask; >+ >+ if (!dev) >+ return device_defaults.gt_types_allowed; >+ >+ mask =3D dev->config.gt_types_allowed; >+ config_group_put(&dev->group); >+ >+ return mask; >+} >+ >+/** >+ * xe_configfs_primary_gt_supported - determine whether primary GTs are s= upported >+ * @xe: xe device >+ * >+ * Return: True if primary GTs are enabled, false if they have been disab= led via >+ * configfs. >+ */ >+bool xe_configfs_primary_gt_supported(struct xe_device *xe) Nitpick: I think it would be more precise if we used _allowed instead of _supported here... I see there are some feedback from Lucas and Michal that could be incorporated. That said, the patch at its current state already looks good to me, so: Reviewed-by: Gustavo Sousa Feel free to keep the r-b when applying any of their suggestions. -- Gustavo Sousa >+{ >+ return (get_gt_types_allowed(xe) & BIT_ULL(XE_GT_TYPE_MAIN)) !=3D= 0; >+} >+ >+/** >+ * xe_configfs_media_gt_supported - determine whether media GTs are suppo= rted >+ * @xe: xe device >+ * >+ * Return: True if the media GTs are enabled, false if they have been dis= abled >+ * via configfs. >+ */ >+bool xe_configfs_media_gt_supported(struct xe_device *xe) >+{ >+ return (get_gt_types_allowed(xe) & BIT_ULL(XE_GT_TYPE_MEDIA)) != =3D 0; >+} >+ > /** > * xe_configfs_get_engines_allowed - get engine allowed mask from configf= s > * @pdev: pci device >diff --git a/drivers/gpu/drm/xe/xe_configfs.h b/drivers/gpu/drm/xe/xe_conf= igfs.h >index c61e0e47ed94..5624e965b911 100644 >--- a/drivers/gpu/drm/xe/xe_configfs.h >+++ b/drivers/gpu/drm/xe/xe_configfs.h >@@ -17,6 +17,8 @@ int xe_configfs_init(void); > void xe_configfs_exit(void); > void xe_configfs_check_device(struct pci_dev *pdev); > bool xe_configfs_get_survivability_mode(struct pci_dev *pdev); >+bool xe_configfs_primary_gt_supported(struct xe_device *xe); >+bool xe_configfs_media_gt_supported(struct xe_device *xe); > u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev); > bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev); > u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev, enum xe_engi= ne_class, >@@ -28,6 +30,8 @@ static inline int xe_configfs_init(void) { return 0; } > static inline void xe_configfs_exit(void) { } > static inline void xe_configfs_check_device(struct pci_dev *pdev) { } > static inline bool xe_configfs_get_survivability_mode(struct pci_dev *pde= v) { return false; } >+static inline bool xe_configfs_primary_gt_supported(struct xe_device *xe)= { return true; } >+static inline bool xe_configfs_media_gt_supported(struct xe_device *xe) {= return true; } > static inline u64 xe_configfs_get_engines_allowed(struct pci_dev *pdev) {= return U64_MAX; } > static inline bool xe_configfs_get_psmi_enabled(struct pci_dev *pdev) { r= eturn false; } > static inline u32 xe_configfs_get_ctx_restore_mid_bb(struct pci_dev *pdev= , enum xe_engine_class, >diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c >index a5932e4f4a23..9c8ab2b41737 100644 >--- a/drivers/gpu/drm/xe/xe_pci.c >+++ b/drivers/gpu/drm/xe/xe_pci.c >@@ -695,6 +695,11 @@ static struct xe_gt *alloc_primary_gt(struct xe_tile = *tile, > struct xe_device *xe =3D tile_to_xe(tile); > struct xe_gt *gt; >=20 >+ if (!xe_configfs_primary_gt_supported(xe)) { >+ drm_info(&xe->drm, "Primary GT disabled via configfs\n"); >+ return NULL; >+ } >+ > gt =3D xe_gt_alloc(tile); > if (IS_ERR(gt)) > return gt; >@@ -720,6 +725,11 @@ static struct xe_gt *alloc_media_gt(struct xe_tile *t= ile, > struct xe_device *xe =3D tile_to_xe(tile); > struct xe_gt *gt; >=20 >+ if (!xe_configfs_media_gt_supported(xe)) { >+ drm_info(&xe->drm, "Media GT disabled via configfs\n"); >+ return NULL; >+ } >+ > if (MEDIA_VER(xe) < 13 || !media_desc) > return NULL; >=20 >@@ -829,6 +839,18 @@ static int xe_info_init(struct xe_device *xe, > if (IS_ERR(tile->primary_gt)) > return PTR_ERR(tile->primary_gt); >=20 >+ /* >+ * It's not currently possible to probe a device with the >+ * primary GT disabled. With some work, this may be futu= re in >+ * the possible for igpu platforms (although probably not= for >+ * dgpu's since access to the primary GT's BCS engines is >+ * required for VRAM management). >+ */ >+ if (!tile->primary_gt) { >+ drm_err(&xe->drm, "Cannot probe device with witho= ut a primary GT\n"); >+ return -ENODEV; >+ } >+ > tile->media_gt =3D alloc_media_gt(tile, media_desc); > if (IS_ERR(tile->media_gt)) > return PTR_ERR(tile->media_gt); >--=20 >2.51.0 >