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Thu, 16 Oct 2025 20:33:34 +0000 Received: from PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350]) by PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350%7]) with mapi id 15.20.9228.011; Thu, 16 Oct 2025 20:33:34 +0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In-Reply-To: <49092d9e223f524bb4a8f478e9cf964a465e7938@intel.com> References: <20251015-xe3p_lpd-basic-enabling-v1-0-d2d1e26520aa@intel.com> <20251015-xe3p_lpd-basic-enabling-v1-14-d2d1e26520aa@intel.com> <49092d9e223f524bb4a8f478e9cf964a465e7938@intel.com> Subject: Re: [PATCH 14/32] drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers From: Gustavo Sousa CC: Ankit Nautiyal , Dnyaneshwar Bhadane , Jouni =?utf-8?q?H=C3=B6gander?= , Juha-pekka Heikkila , Luca Coelho , Lucas De Marchi , Matt Atwood , Matt Roper , "Ravi Kumar Vodapalli" , Sai Teja Pottumuttu , Shekhar Chauhan , Vinod Govindapillai To: Jani Nikula , , Date: Thu, 16 Oct 2025 17:33:30 -0300 Message-ID: <176064681063.2362.656250585777379141@intel.com> User-Agent: alot/0.12.dev22+g972188619 X-ClientProxiedBy: BYAPR11CA0065.namprd11.prod.outlook.com (2603:10b6:a03:80::42) To PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8287:EE_|PH7PR11MB6955:EE_ X-MS-Office365-Filtering-Correlation-Id: ffa4ada3-2966-4898-5b18-08de0cf34714 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|1800799024; 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Update the changed fields in the driver. >> Below are the changes: >> >> MBUS_CTL: >> Translation Throttle Min >> It changed from BIT[15:13] to BIT[16:13] >> >> DBUF_CTL: >> Min Tracker State Service >> It changed from BIT[18:16] to BIT[20:16] >> Max Tracker State Service >> It changed to from BIT[23:19] to BIT[14:10] >> but using default value, so no need to define >> in code. >> >> Bspec: 68868, 68872 >> Signed-off-by: Ravi Kumar Vodapalli >> Signed-off-by: Gustavo Sousa >> --- >> drivers/gpu/drm/i915/display/skl_watermark.c | 16 ++++++++++++---- >> drivers/gpu/drm/i915/display/skl_watermark_regs.h | 12 ++++++++++-- >> 2 files changed, 22 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/= drm/i915/display/skl_watermark.c >> index 9df9ee137bf9..41f64e347436 100644 >> --- a/drivers/gpu/drm/i915/display/skl_watermark.c >> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c >> @@ -3505,7 +3505,10 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct i= ntel_display *display, >> if (!HAS_MBUS_JOINING(display)) >> return; >> =20 >> - if (DISPLAY_VER(display) >=3D 20) >> + if (DISPLAY_VER(display) >=3D 35) >> + intel_de_rmw(display, MBUS_CTL, XE3P_MBUS_TRANSLATION_T= HROTTLE_MIN_MASK, >> + XE3P_MBUS_TRANSLATION_THROTTLE_MIN(ratio -= 1)); >> + else if (DISPLAY_VER(display) >=3D 20) >> intel_de_rmw(display, MBUS_CTL, MBUS_TRANSLATION_THROTT= LE_MIN_MASK, >> MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1)); >> =20 >> @@ -3516,9 +3519,14 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct i= ntel_display *display, >> ratio, str_yes_no(joined_mbus)); >> =20 >> for_each_dbuf_slice(display, slice) >> - intel_de_rmw(display, DBUF_CTL_S(slice), >> - DBUF_MIN_TRACKER_STATE_SERVICE_MASK, >> - DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1))= ; >> + if (DISPLAY_VER(display) >=3D 35) >> + intel_de_rmw(display, DBUF_CTL_S(slice), >> + XE3P_DBUF_MIN_TRACKER_STATE_SERVIC= E_MASK, >> + XE3P_DBUF_MIN_TRACKER_STATE_SERVIC= E(ratio - 1)); >> + else >> + intel_de_rmw(display, DBUF_CTL_S(slice), >> + DBUF_MIN_TRACKER_STATE_SERVICE_MAS= K, >> + DBUF_MIN_TRACKER_STATE_SERVICE(rat= io - 1)); >> } >> =20 >> static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_sta= te *state) >> diff --git a/drivers/gpu/drm/i915/display/skl_watermark_regs.h b/drivers= /gpu/drm/i915/display/skl_watermark_regs.h >> index c5572fc0e847..7e0877303e05 100644 >> --- a/drivers/gpu/drm/i915/display/skl_watermark_regs.h >> +++ b/drivers/gpu/drm/i915/display/skl_watermark_regs.h >> @@ -41,7 +41,11 @@ >> #define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBU= S_JOIN_PIPE_SELECT_MASK, pipe) >> #define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELE= CT(7) >> #define MBUS_TRANSLATION_THROTTLE_MIN_MASK REG_GENMASK(15, 13) >> -#define MBUS_TRANSLATION_THROTTLE_MIN(val) REG_FIELD_PREP(MBUS= _TRANSLATION_THROTTLE_MIN_MASK, val) >> +#define MBUS_TRANSLATION_THROTTLE_MIN(val) \ >> + REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val) >> +#define XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK REG_GENMASK(16= , 13) >> +#define XE3P_MBUS_TRANSLATION_THROTTLE_MIN(val) \ >> + REG_FIELD_PREP(XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK,= val) >> =20 >> /* >> * The below are numbered starting from "S1" on gen11/gen12, but starti= ng >> @@ -65,7 +69,11 @@ >> #define DBUF_TRACKER_STATE_SERVICE_MASK REG_GENMASK(23, 19) >> #define DBUF_TRACKER_STATE_SERVICE(x) REG_FIELD_PREP(DB= UF_TRACKER_STATE_SERVICE_MASK, x) >> #define DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(18, 16)= /* ADL-P+ */ >> -#define DBUF_MIN_TRACKER_STATE_SERVICE(x) REG_FIELD_PRE= P(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */ >> +#define DBUF_MIN_TRACKER_STATE_SERVICE(x) \ >> + REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) = /* ADL-P+ */ >> +#define XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK REG_GENMASK(20= , 16) >> +#define XE3P_DBUF_MIN_TRACKER_STATE_SERVICE(x) \ >> + REG_FIELD_PREP(XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK= , x) > >Please just keep the long lines in this file. In this case, I think it's >cleaner. Alright, done. Because of the length of the new XE3P_* macros, the column alignment for the definition is off by 1 tab character w.r.t. to the items above them. I took a guess and aligned the already existing ones with one extra tab for each. Let me know if that's fine to you. These changes are in still my local tree as I incorporate the remaining of the review feedback (and also wait a bit more for more feedback). -- Gustavo Sousa > > >> =20 >> #define MTL_LATENCY_LP0_LP1 _MMIO(0x45780) >> #define MTL_LATENCY_LP2_LP3 _MMIO(0x45784) > >--=20 >Jani Nikula, Intel