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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) by SJ2PR11MB8299.namprd11.prod.outlook.com (2603:10b6:a03:53f::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.16; Mon, 10 Nov 2025 22:18:29 +0000 Received: from PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350]) by PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350%7]) with mapi id 15.20.9298.015; Mon, 10 Nov 2025 22:18:29 +0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In-Reply-To: References: <20251107-xe3p_lpd-basic-enabling-v4-0-ab3367f65f15@intel.com> <20251107-xe3p_lpd-basic-enabling-v4-5-ab3367f65f15@intel.com> <20251110163503.GD4063759@mdroper-desk1.amr.corp.intel.com> Subject: Re: [PATCH v4 05/11] drm/i915/fbc: Add intel_fbc_id_for_pipe() From: Gustavo Sousa CC: , , "Ankit Nautiyal" , Dnyaneshwar Bhadane , Jouni =?utf-8?q?H=C3=B6gander?= , Juha-pekka Heikkila , Luca Coelho , Lucas De Marchi , Matt Atwood , Ravi Kumar Vodapalli , Shekhar Chauhan , Vinod Govindapillai To: Ville =?utf-8?b?U3lyasOkbMOk?= , Matt Roper Date: Mon, 10 Nov 2025 19:18:25 -0300 Message-ID: <176281310529.2999.16445497165397082799@intel.com> User-Agent: alot/0.12.dev22+g972188619 X-ClientProxiedBy: SJ0PR03CA0036.namprd03.prod.outlook.com (2603:10b6:a03:33e::11) To PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8287:EE_|SJ2PR11MB8299:EE_ X-MS-Office365-Filtering-Correlation-Id: 3456253f-f0b2-4382-19d6-08de20a71362 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|366016; 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Let's promote the static function skl_fbc_id_for_pipe() to= a >> > public one named intel_fbc_id_for_pipe(). >> >=20 >> > Signed-off-by: Gustavo Sousa >> > --- >> > drivers/gpu/drm/i915/display/intel_fbc.c | 5 +++++ >> > drivers/gpu/drm/i915/display/intel_fbc.h | 2 ++ >> > drivers/gpu/drm/i915/display/skl_universal_plane.c | 9 ++------- >> > 3 files changed, 9 insertions(+), 7 deletions(-) >> >=20 >> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/dr= m/i915/display/intel_fbc.c >> > index a1e3083022ee..435bfd05109c 100644 >> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c >> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c >> > @@ -129,6 +129,11 @@ struct intel_fbc { >> > const char *no_fbc_reason; >> > }; >> > =20 >> > +enum intel_fbc_id intel_fbc_id_for_pipe(enum pipe pipe) >> > +{ >> > + return pipe - PIPE_A + INTEL_FBC_A; >>=20 >> The existing usage of skl_fbc_id_for_pipe() was to call this function to >> receive a (possibly bogus) FBC ID, and then follow up with a call to >> skl_plane_has_fbc() which had checks to make sure the returned FBC ID >> actually existed on the platform. So, for example, calling >> skl_fbc_id_for_pipe(PIPE_B) on something like an ICL would return >> INTEL_FBC_B here, but then the subsequent call to skl_plane_has_fbc() >> would realize that there is no FBC_B on that platform and bail out. >> It's only relatively recently (MTL and beyond I think?) that FBC has >> become usable on pipes other than A. >>=20 >> Now that we're promoting this function to be more general, should we >> also adjust the logic so that this function either returns a *valid* FBC >> ID or and error? Otherwise it may not be apparent to people writing new >> code that the result returned here can't be immediately trusted without >> additional checking. > >The simples way to find the FBC instance for a pipe is to grab it from >the primary plane. That is already used elsewhere so won't make things >any less generic. And do that internally without a public function, right? Because the feedback in the next patch is that the part that handles the "FBC decompressing" bit should be in intel_fbc.c. How should the primary plane be found? Loop with for_each_intel_plane_on_crtc() and get the one with type DRM_PLANE_TYPE_PRIMARY? For example: static struct intel_fbc *intel_fbc_for_pipe(struct intel_display *displ= ay, enum pipe pipe) { struct intel_crtc *crtc =3D intel_crtc_for_pipe(display, pipe); struct intel_plane *primary =3D NULL; struct intel_plane *plane; for_each_intel_plane_on_crtc(display->drm, crtc, plane) { if (plane->base.type =3D=3D DRM_PLANE_TYPE_PRIMARY) { primary =3D plane; break; } } if (drm_WARN_ON(display->drm, primary =3D=3D NULL)) return NULL; return primary->fbc; } I saw that the DRM layer keeps a "primary" plane in struct drm_crtc, but, reading the kerneldoc for that member, I get the feeling that we should not use it. -- Gustavo Sousa > >>=20 >>=20 >> Matt >>=20 >> > +} >> > + >> > /* plane stride in pixels */ >> > static unsigned int intel_fbc_plane_stride(const struct intel_plane_s= tate *plane_state) >> > { >> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/dr= m/i915/display/intel_fbc.h >> > index 91424563206a..3d02f3fe5630 100644 >> > --- a/drivers/gpu/drm/i915/display/intel_fbc.h >> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.h >> > @@ -9,6 +9,7 @@ >> > #include >> > =20 >> > enum fb_op_origin; >> > +enum pipe; >> > struct intel_atomic_state; >> > struct intel_crtc; >> > struct intel_crtc_state; >> > @@ -27,6 +28,7 @@ enum intel_fbc_id { >> > I915_MAX_FBCS, >> > }; >> > =20 >> > +enum intel_fbc_id intel_fbc_id_for_pipe(enum pipe pipe); >> > int intel_fbc_atomic_check(struct intel_atomic_state *state); >> > int intel_fbc_min_cdclk(const struct intel_crtc_state *crtc_state); >> > bool intel_fbc_pre_update(struct intel_atomic_state *state, >> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/driv= ers/gpu/drm/i915/display/skl_universal_plane.c >> > index bc55fafe9ce3..275ee2903219 100644 >> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c >> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c >> > @@ -439,11 +439,6 @@ static int skl_plane_max_height(const struct drm_= framebuffer *fb, >> > return 4096; >> > } >> > =20 >> > -static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe) >> > -{ >> > - return pipe - PIPE_A + INTEL_FBC_A; >> > -} >> > - >> > static bool skl_plane_has_fbc(struct intel_display *display, >> > enum intel_fbc_id fbc_id, enum plane_id= plane_id) >> > { >> > @@ -896,7 +891,7 @@ static void x3p_lpd_plane_update_pixel_normalizer(= struct intel_dsb *dsb, >> > bool enable) >> > { >> > struct intel_display *display =3D to_intel_display(plane); >> > - enum intel_fbc_id fbc_id =3D skl_fbc_id_for_pipe(plane->pipe)= ; >> > + enum intel_fbc_id fbc_id =3D intel_fbc_id_for_pipe(plane->pip= e); >> > u32 val; >> > =20 >> > /* Only HDR planes have pixel normalizer and don't matter if = no FBC */ >> > @@ -2442,7 +2437,7 @@ void icl_link_nv12_planes(struct intel_plane_sta= te *uv_plane_state, >> > static struct intel_fbc *skl_plane_fbc(struct intel_display *display, >> > enum pipe pipe, enum plane_id = plane_id) >> > { >> > - enum intel_fbc_id fbc_id =3D skl_fbc_id_for_pipe(pipe); >> > + enum intel_fbc_id fbc_id =3D intel_fbc_id_for_pipe(pipe); >> > =20 >> > if (skl_plane_has_fbc(display, fbc_id, plane_id)) >> > return display->fbc[fbc_id]; >> >=20 >> > --=20 >> > 2.51.0 >> >=20 >>=20 >> --=20 >> Matt Roper >> Graphics Software Engineer >> Linux GPU Platform Enablement >> Intel Corporation > >--=20 >Ville Syrj=C3=A4l=C3=A4 >Intel