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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) by PH7PR11MB7074.namprd11.prod.outlook.com (2603:10b6:510:20d::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9478.4; Mon, 5 Jan 2026 14:37:27 +0000 Received: from PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350]) by PH8PR11MB8287.namprd11.prod.outlook.com ([fe80::7e8b:2e5:8ce4:2350%3]) with mapi id 15.20.9478.004; Mon, 5 Jan 2026 14:37:26 +0000 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable In-Reply-To: References: <20251230083142.70064-1-suraj.kandpal@intel.com> <20251230083142.70064-3-suraj.kandpal@intel.com> <176710816443.18661.15779385817780893127@intel.com> Subject: RE: [PATCH 2/3] drm/i915/cx0: Move step 12 to enable clock hook From: Gustavo Sousa CC: "Nautiyal, Ankit K" , "Kahola, Mika" To: "Kandpal, Suraj" , "intel-gfx@lists.freedesktop.org" , "intel-xe@lists.freedesktop.org" Date: Mon, 5 Jan 2026 11:37:22 -0300 Message-ID: <176762384242.9480.14418194462966711746@intel.com> User-Agent: alot/0.12.dev22+g972188619 X-ClientProxiedBy: SJ0PR13CA0095.namprd13.prod.outlook.com (2603:10b6:a03:2c5::10) To PH8PR11MB8287.namprd11.prod.outlook.com (2603:10b6:510:1c7::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR11MB8287:EE_|PH7PR11MB7074:EE_ X-MS-Office365-Filtering-Correlation-Id: a1e0547e-5204-47b1-0777-08de4c67f255 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014; 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Had this been just movement >of step 12 then I would have squashed them. Hm... The previous patch is introducing intel_cx0pll_enable_clock() and says it is splitting the sequence in two, but then it ended up is leaving step 12 behind. If it is introducing intel_cx0pll_enable_clock(), it could as well have done it with a signature that allows step 12 to be done. IMO, here we are modifying that function to "make it right". This looks like a good fixup candidate to me. -- Gustavo Sousa > >Regards, >Suraj Kandpal > >>=20 >> -- >> Gustavo Sousa >>=20 >> > >> >Signed-off-by: Suraj Kandpal >> >--- >> > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 37 ++++++++++---------- >> > 1 file changed, 19 insertions(+), 18 deletions(-) >> > >> >diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c >> >b/drivers/gpu/drm/i915/display/intel_cx0_phy.c >> >index f3baba264e88..5edd293b533b 100644 >> >--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c >> >+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c >> >@@ -3281,21 +3281,6 @@ static void intel_cx0pll_enable(struct >> intel_encoder *encoder, >> > */ >> > intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), >> >port_clock); >> > >> >- /* >> >- * 12. Toggle powerdown if HDMI is enabled on C10 PHY. >> >- * >> >- * Wa_13013502646: >> >- * Fixes: HDMI lane to lane skew violations on C10 display PHY= s. >> >- * Workaround: Toggle powerdown value by setting first to P0 a= nd then >> to P2, for both >> >- * PHY lanes. >> >- */ >> >- if (!cx0pll_state_is_dp(pll_state) && pll_state->use_c10) { >> >- intel_cx0_powerdown_change_sequence(encoder, >> INTEL_CX0_BOTH_LANES, >> >- XELPDP_P0_STATE_AC= TIVE); >> >- intel_cx0_powerdown_change_sequence(encoder, >> INTEL_CX0_BOTH_LANES, >> >- XELPDP_P2_STATE_RE= ADY); >> >- } >> >- >> > intel_cx0_phy_transaction_end(encoder, wakeref); } >> > >> >@@ -3379,7 +3364,8 @@ static int intel_mtl_tbt_clock_select(struct >> intel_display *display, >> > } >> > } >> > >> >-static void intel_cx0pll_enable_clock(struct intel_encoder *encoder) >> >+static void intel_cx0pll_enable_clock(struct intel_encoder *encoder, >> >+ const struct intel_cx0pll_state >> >+*pll_state) >> > { >> > struct intel_display *display =3D to_intel_display(encoder); >> > enum phy phy =3D intel_encoder_to_phy(encoder); @@ -3412,6 >> >+3398,21 @@ static void intel_cx0pll_enable_clock(struct intel_encoder >> *encoder) >> > * Frequency Change. We handle this step in bxt_set_cdclk(). >> > */ >> > >> >+ /* >> >+ * 12. Toggle powerdown if HDMI is enabled on C10 PHY. >> >+ * >> >+ * Wa_13013502646: >> >+ * Fixes: HDMI lane to lane skew violations on C10 display PHY= s. >> >+ * Workaround: Toggle powerdown value by setting first to P0 a= nd then >> to P2, for both >> >+ * PHY lanes. >> >+ */ >> >+ if (!cx0pll_state_is_dp(pll_state) && pll_state->use_c10) { >> >+ intel_cx0_powerdown_change_sequence(encoder, >> INTEL_CX0_BOTH_LANES, >> >+ XELPDP_P0_STATE_AC= TIVE); >> >+ intel_cx0_powerdown_change_sequence(encoder, >> INTEL_CX0_BOTH_LANES, >> >+ XELPDP_P2_STATE_RE= ADY); >> >+ } >> >+ >> > intel_cx0_phy_transaction_end(encoder, wakeref); } >> > >> >@@ -3485,7 +3486,7 @@ void intel_mtl_pll_enable_clock(struct >> intel_encoder *encoder, >> > if (intel_tc_port_in_tbt_alt_mode(dig_port)) >> > intel_mtl_tbt_pll_enable_clock(encoder, crtc_state->po= rt_clock); >> > else >> >- intel_cx0pll_enable_clock(encoder); >> >+ intel_cx0pll_enable_clock(encoder, >> >+ &crtc_state->dpll_hw_state.cx0pll); >> > } >> > >> > /* >> >@@ -3808,7 +3809,7 @@ void intel_cx0_pll_power_save_wa(struct >> intel_display *display) >> > encoder->base.base.id, >> >encoder->base.name); >> > >> > intel_cx0pll_enable(encoder, &pll_state); >> >- intel_cx0pll_enable_clock(encoder); >> >+ intel_cx0pll_enable_clock(encoder, &pll_state); >> > intel_cx0pll_disable(encoder); >> > intel_cx0pll_disable_clock(encoder); >> > } >> >-- >> >2.34.1 >> >