Re: [Intel-xe] [PATCH v2 09/10] drm/xe: Clear SOC CORRECTABLE error registers.

[Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>]

On 18/10/23 09:30, Himal Prasad Ghimiray wrote:
> PVC doesn't support correctable SOC error reporting, classify them as
> Undefined and clear the registers.
>
> v2
> - Fix commit message.
> - Although the errors are correctable but they are spurious interrupt.
> Hence use drm_err instead of drm_warn.(Aravind)
>
> Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
> Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_hw_error.c | 23 +++++++++++++++++++++--
>  1 file changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_hw_error.c b/drivers/gpu/drm/xe/xe_hw_error.c
> index 62b4051c6633..5700f708425f 100644
> --- a/drivers/gpu/drm/xe/xe_hw_error.c
> +++ b/drivers/gpu/drm/xe/xe_hw_error.c
> @@ -646,8 +646,26 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>  	if (tile_to_xe(tile)->info.platform != XE_PVC)
>  		return;
>  
> -	if (hw_err == HARDWARE_ERROR_CORRECTABLE)
> -		return;
> +	if (hw_err == HARDWARE_ERROR_CORRECTABLE) {
> +		for (i = 0; i < XE_SOC_NUM_IEH; i++)
> +			xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
> +					~REG_BIT(hw_err));
> +
> +		xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
> +				REG_GENMASK(31, 0));
> +		xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_MASTER_REG(base, hw_err),
> +				REG_GENMASK(31, 0));
> +		xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
> +				REG_GENMASK(31, 0));
> +		xe_mmio_write32(gt, SOC_LOCAL_ERR_STAT_SLAVE_REG(slave_base, hw_err),
> +				REG_GENMASK(31, 0));
> +
> +		drm_err(&tile_to_xe(tile)->drm, HW_ERR
> +			"Tile%d reported Undefine SOC CORRECTABLE error.",
> +			tile->id);
> +
> +		goto unmask_gsysevtctl;
> +	}
>  
>  	base = SOC_PVC_BASE;
>  	slave_base = SOC_PVC_SLAVE_BASE;
> @@ -729,6 +747,7 @@ xe_soc_hw_error_handler(struct xe_tile *tile, const enum hardware_error hw_err)
>  	xe_mmio_write32(gt, SOC_GLOBAL_ERR_STAT_MASTER_REG(base, hw_err),
>  			mst_glb_errstat);
>  
> +unmask_gsysevtctl:
>  	for (i = 0; i < XE_SOC_NUM_IEH; i++)
>  		xe_mmio_write32(gt, SOC_GSYSEVTCTL_REG(base, slave_base, i),
>  				(HARDWARE_ERROR_MAX << 1) + 1);

Reviewed-by: Aravind Iddamsetty <aravind.iddamsetty@linux.intel.com>

Thanks,
Aravind.