Re: [PATCH 6/8] drm/xe/xe_ras: Add structures and commands for Uncorrectable Core Compute Errors

[Riana Tauro <riana.tauro@intel.com>]

On 2/23/2026 7:49 PM, Mallesh, Koujalagi wrote:
> 
> On 22-01-2026 03:36 pm, Riana Tauro wrote:
>> Add the sysctrl commands and response structures for Uncorrectable
>> Core Compute errors.
>>
>> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
>> ---
>>   drivers/gpu/drm/xe/xe_ras.c                   |  53 +++++++
>>   drivers/gpu/drm/xe/xe_ras_types.h             | 131 ++++++++++++++++++
>>   drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h |  13 ++
>>   3 files changed, 197 insertions(+)
>>   create mode 100644 drivers/gpu/drm/xe/xe_ras_types.h
>>
>> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
>> index ba5ed37aed28..ace08d8d8d46 100644
>> --- a/drivers/gpu/drm/xe/xe_ras.c
>> +++ b/drivers/gpu/drm/xe/xe_ras.c
>> @@ -4,9 +4,62 @@
>>    */
>>   #include <linux/pci.h>
>> +#include "xe_assert.h"
>>   #include "xe_device_types.h"
>>   #include "xe_ras.h"
>> +/* Severity classification of detected errors */
>> +enum xe_ras_severity {
>> +    XE_RAS_SEVERITY_NOT_SUPPORTED = 0,
>> +    XE_RAS_SEVERITY_CORRECTABLE,
>> +    XE_RAS_SEVERITY_UNCORRECTABLE,
>> +    XE_RAS_SEVERITY_INFORMATIONAL,
>> +    XE_RAS_SEVERITY_MAX
>> +};
>> +
>> +/* major IP blocks where errors can originate */
>> +enum xe_ras_component {
>> +    XE_RAS_COMPONENT_NOT_SUPPORTED = 0,
>> +    XE_RAS_COMPONENT_DEVICE_MEMORY,
>> +    XE_RAS_COMPONENT_CORE_COMPUTE,
>> +    XE_RAS_COMPONENT_RESERVED,
>> +    XE_RAS_COMPONENT_PCIE,
>> +    XE_RAS_COMPONENT_FABRIC,
>> +    XE_RAS_COMPONENT_SOC,
>> +    XE_RAS_COMPONENT_MAX
>> +};
>> +
>> +static const char * const xe_ras_severities[] = {
>> +    [XE_RAS_SEVERITY_NOT_SUPPORTED]        = "Not Supported",
>> +    [XE_RAS_SEVERITY_CORRECTABLE]        = "Correctable",
>> +    [XE_RAS_SEVERITY_UNCORRECTABLE]        = "Uncorrectable",
>> +    [XE_RAS_SEVERITY_INFORMATIONAL]        = "Informational",
>> +};
>> +
>> +static const char * const xe_ras_components[] = {
>> +    [XE_RAS_COMPONENT_NOT_SUPPORTED]    = "Not Supported",
>> +    [XE_RAS_COMPONENT_DEVICE_MEMORY]    = "Device Memory",
>> +    [XE_RAS_COMPONENT_CORE_COMPUTE]        = "Core Compute",
>> +    [XE_RAS_COMPONENT_RESERVED]        = "Reserved",
>> +    [XE_RAS_COMPONENT_PCIE]            = "PCIe",
>> +    [XE_RAS_COMPONENT_FABRIC]        = "Fabric",
>> +    [XE_RAS_COMPONENT_SOC]            = "SoC",
>> +};
>> +
>> +static inline const char *severity_to_str(struct xe_device *xe, u32 
>> severity)
>> +{
>> +    xe_assert(xe, severity < XE_RAS_SEVERITY_MAX);
>> +
>> +    return xe_ras_severities[severity];
>> +}
>> +
>> +static inline const char *comp_to_str(struct xe_device *xe, u32 comp)
>> +{
>> +    xe_assert(xe, comp < XE_RAS_COMPONENT_MAX);
>> +
>> +    return xe_ras_components[comp];
>> +}
>> +
>>   #ifdef CONFIG_PCIEAER
>>   static void unmask_and_downgrade_internal_error(struct xe_device *xe)
>>   {
>> diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/ 
>> xe_ras_types.h
>> new file mode 100644
>> index 000000000000..c7a930c16f68
>> --- /dev/null
>> +++ b/drivers/gpu/drm/xe/xe_ras_types.h
>> @@ -0,0 +1,131 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Copyright © 2026 Intel Corporation
>> + */
>> +
>> +#ifndef _XE_RAS_TYPES_H_
>> +#define _XE_RAS_TYPES_H_
>> +
>> +#include <linux/types.h>
>> +
>> +#define XE_RAS_MAX_ERROR_DETAILS    16
>> +
>> +/**
>> + * struct xe_ras_error_common - Common RAS error class
>> + *
>> + * This structure contains error severity and component information
>> + * across all products
>> + */
>> +struct xe_ras_error_common {
>> +    /** @severity: Error Severity */
>> +    u8 severity;
>> +    /** @component: IP where the error originated */
>> +    u8 component;
>> +} __packed;
>> +
>> +/**
>> + * struct xe_ras_error_unit - Error unit information
>> + */
>> +struct xe_ras_error_unit {
>> +    /** @tile: Tile identifier */
>> +    u8 tile;
>> +    /** @instance: Instance identifier within a component */
>> +    u32 instance;
>> +} __packed;
> Performance penalty for accessing unaligned u32.

These are response structures from firmware.
will check

>> +
>> +/**
>> + * struct xe_ras_error_cause - Error cause information
>> + */
>> +struct xe_ras_error_cause {
>> +    /** @cause: Cause */
>> +    u32 cause;
>> +    /** @reserved: For future use */
>> +    u8 reserved;
>> +} __packed;
>> +
>> +/**
>> + * struct xe_ras_error_product - Error fields that are specific to 
>> the product
>> + */
>> +struct xe_ras_error_product {
>> +    /** @unit: Unit within IP block */
>> +    struct xe_ras_error_unit unit;
>> +    /** @error_cause: Cause/checker */
>> +    struct xe_ras_error_cause error_cause;
>> +} __packed;
>> +
>> +/**
>> + * struct xe_ras_error_class - Complete RAS Error Class
>> + *
>> + * This structure provides the complete error classification by 
>> combining
>> + * the common error class with the product-specific error class.
>> + */
>> +struct xe_ras_error_class {
>> +    /** @common: Common error severity and component */
>> +    struct xe_ras_error_common common;
>> +    /** @product: Product-specific unit and cause */
>> +    struct xe_ras_error_product product;
>> +} __packed;
>> +
>> +/**
>> + * struct xe_ras_error_array - Details of the error types
>> + */
>> +struct xe_ras_error_array {
>> +    /** @error_class: Error class */
>> +    struct xe_ras_error_class error_class;
>> +    /** @timestamp: Timestamp */
>> +    u64 timestamp;
>> +    /** @error_details: Error details specific to the class */
>> +    u32 error_details[XE_RAS_MAX_ERROR_DETAILS];
>> +} __packed;
>> +
>> +/**
>> + * struct xe_ras_get_error_response - Response for 
>> XE_SYSCTRL_GET_SOC_ERROR
>> + */
>> +struct xe_ras_get_error_response {
>> +    /** @num_errors: No of errors reported in this response */
>> +    u8 num_errors;
>> +    /** @additional_errors: Indicates if the errors are pending */
>> +    u8 additional_errors;
>> +    /** @error_arr: Array of up to 3 errors */
>> +    struct xe_ras_error_array error_arr[3];
> 
> Use a Macro for a magic number 3.

Sure. Will fix

Thanks
Riana


> 
> Thanks
> 
> -/Mallesh
> 
>> +} __packed;
>> +
>> +/**
>> + * struct xe_ras_compute_error: Error details of Compute error
>> + */
>> +struct xe_ras_compute_error {
>> +    /** @error_log_header: Error Source and type */
>> +    u32 error_log_header;
>> +    /** @internal_error_log: Internal Error log */
>> +    u32 internal_error_log;
>> +    /** @fabric_log: Fabric Error log */
>> +    u32 fabric_log;
>> +    /** @internal_error_addr_log0: Internal Error addr log */
>> +    u32 internal_error_addr_log0;
>> +    /** @internal_error_addr_log1: Internal Error addr log */
>> +    u32 internal_error_addr_log1;
>> +    /** @packet_log0: Packet log */
>> +    u32 packet_log0;
>> +    /** @packet_log1: Packet log */
>> +    u32 packet_log1;
>> +    /** @packet_log2: Packet log */
>> +    u32 packet_log2;
>> +    /** @packet_log3: Packet log */
>> +    u32 packet_log3;
>> +    /** @packet_log4: Packet log */
>> +    u32 packet_log4;
>> +    /** @misc_log0: Misc log */
>> +    u32 misc_log0;
>> +    /** @misc_log1: Misc log */
>> +    u32 misc_log1;
>> +    /** @spare_log0: Spare log */
>> +    u32 spare_log0;
>> +    /** @spare_log1: Spare log */
>> +    u32 spare_log1;
>> +    /** @spare_log2: Spare log */
>> +    u32 spare_log2;
>> +    /** @spare_log3: Spare log */
>> +    u32 spare_log3;
>> +} __packed;
>> +
>> +#endif
>> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/ 
>> gpu/drm/xe/xe_sysctrl_mailbox_types.h
>> index 1f315ad1b996..45ef10f5cfa2 100644
>> --- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
>> +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
>> @@ -8,6 +8,19 @@
>>   #include <linux/types.h>
>> +/**
>> + * enum xe_sysctrl_mailbox_command_id - RAS Command ID's for GFSP group
>> + *
>> + * @XE_SYSCTRL_CMD_GET_SOC_ERROR: Get basic error information
>> + */
>> +enum xe_sysctrl_mailbox_command_id {
>> +    XE_SYSCTRL_CMD_GET_SOC_ERROR = 1
>> +};
>> +
>> +enum xe_sysctrl_group {
>> +    XE_SYSCTRL_GROUP_GFSP = 1
>> +};
>> +
>>   struct xe_sysctrl_mailbox_mkhi_msg_hdr {
>>       __le32 data;
>>   } __packed;