From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F0567EB64DC for ; Tue, 27 Jun 2023 10:23:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B5F5010E2DD; Tue, 27 Jun 2023 10:23:05 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6F09910E2DD for ; Tue, 27 Jun 2023 10:23:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1687861383; x=1719397383; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9B2eHrC4ufBKlXOUIjJlJcJfVOKRe98Bt9FMhKPYKj4=; b=H5fm2vKel9loozddr9TC7dNLTf70IVOI5ZYIebCXlp1L6BNq4fqHlpUu tdgIpmCpHUvBql1Cts4Wv6Q4nU5UupXn7Y1nKtmYx7br+ecSRD2ga+Trh Kgp6F738A/wnQUlEaqKyBT3K1saf5pnKG3GNRCxAgn7axq+apUnmCHT1S 6jqg2n4C0eqDSj+2GDhcjg3FjiQy4/RX61A8fKqWJ/UeDMSquRRSo30p8 6lkF49EJvCHweChdI1uhS9U5CJHvd6xaJ9Hhn6DYEMlvsghxoWYXv3GcM wr70PSGDuAMos5PTVwLIIwaCOVoBa+xQTF6wYiEI3OU0mhmNVNKfCg54q A==; X-IronPort-AV: E=McAfee;i="6600,9927,10753"; a="346295437" X-IronPort-AV: E=Sophos;i="6.01,162,1684825200"; d="scan'208";a="346295437" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2023 03:23:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10753"; a="840649524" X-IronPort-AV: E=Sophos;i="6.01,162,1684825200"; d="scan'208";a="840649524" Received: from jwerner6-mobl.ger.corp.intel.com (HELO localhost) ([10.252.39.48]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Jun 2023 03:23:01 -0700 From: Jani Nikula To: intel-xe@lists.freedesktop.org Date: Tue, 27 Jun 2023 13:22:22 +0300 Message-Id: <20230627102223.260893-5-jani.nikula@intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230627102223.260893-1-jani.nikula@intel.com> References: <20230627102223.260893-1-jani.nikula@intel.com> MIME-Version: 1.0 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Content-Transfer-Encoding: 8bit Subject: [Intel-xe] [PATCH 4/5] fixup! drm/xe/display: Implement display support X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jani.nikula@intel.com, lucas.demarchi@intel.com Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Add raw_reg_* accessors and use them. Signed-off-by: Jani Nikula --- .../drm/xe/compat-i915-headers/intel_uncore.h | 24 +++++++++++++++++++ drivers/gpu/drm/xe/display/ext/i915_irq.c | 15 ++---------- 2 files changed, 26 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h index 652654b5481d..a46dca558366 100644 --- a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h +++ b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h @@ -140,4 +140,28 @@ static inline void intel_uncore_write_notrace(struct intel_uncore *uncore, xe_mmio_write32(__compat_uncore_to_gt(uncore), reg, val); } +static inline void __iomem *intel_uncore_regs(struct intel_uncore *uncore) +{ + struct xe_device *xe = container_of(uncore, struct xe_device, uncore); + + return xe_device_get_root_tile(xe)->mmio.regs; +} + +/* + * The raw_reg_{read,write} macros are intended as a micro-optimization for + * interrupt handlers so that the pointer indirection on uncore->regs can + * be computed once (and presumably cached in a register) instead of generating + * extra load instructions for each MMIO access. + * + * Given that these macros are only intended for non-GSI interrupt registers + * (and the goal is to avoid extra instructions generated by the compiler), + * these macros do not account for uncore->gsi_offset. Any caller that needs + * to use these macros on a GSI register is responsible for adding the + * appropriate GSI offset to the 'base' parameter. + */ +#define raw_reg_read(base, reg) \ + readl(base + i915_mmio_reg_offset(reg)) +#define raw_reg_write(base, reg, value) \ + writel(value, base + i915_mmio_reg_offset(reg)) + #endif /* __INTEL_UNCORE_H__ */ diff --git a/drivers/gpu/drm/xe/display/ext/i915_irq.c b/drivers/gpu/drm/xe/display/ext/i915_irq.c index 6235ff9dec36..157403d1d8fe 100644 --- a/drivers/gpu/drm/xe/display/ext/i915_irq.c +++ b/drivers/gpu/drm/xe/display/ext/i915_irq.c @@ -35,8 +35,10 @@ #include #include "i915_drv.h" +#include "i915_irq.h" #include "i915_reg.h" #include "icl_dsi_regs.h" +#include "intel_clock_gating.h" #include "intel_display_trace.h" #include "intel_display_types.h" #include "intel_dp_aux.h" @@ -48,19 +50,6 @@ #include "intel_psr_regs.h" #include "intel_uncore.h" -static u32 raw_reg_read(void __iomem *base, i915_reg_t reg) -{ - return readl(base + reg.reg); -} - -static void raw_reg_write(void __iomem *base, i915_reg_t reg, u32 value) -{ - writel(value, base + reg.reg); -} - -#include "i915_irq.h" -#include "intel_clock_gating.h" - static void gen3_irq_reset(struct xe_device *dev_priv, i915_reg_t imr, i915_reg_t iir, i915_reg_t ier) { -- 2.39.2