From: Matthew Auld <matthew.auld@intel.com>
To: intel-xe@lists.freedesktop.org
Subject: [Intel-xe] [PATCH v6 07/11] drm/xe/gt: tweak placement for signalling TLB fences after GT reset
Date: Mon, 10 Jul 2023 10:40:45 +0100 [thread overview]
Message-ID: <20230710094037.28179-20-matthew.auld@intel.com> (raw)
In-Reply-To: <20230710094037.28179-13-matthew.auld@intel.com>
Assumption here is that submission is disabled along with CT, and full
GT reset will also nuke TLBs, so should be safe to signal all in-flight
TLB fences, but only after the actual reset so move the placement
slightly.
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
---
drivers/gpu/drm/xe/xe_gt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index bc76678a8276..a21d44bfe9e8 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -519,7 +519,6 @@ static int gt_reset(struct xe_gt *gt)
xe_uc_stop_prepare(>->uc);
xe_gt_pagefault_reset(gt);
- xe_gt_tlb_invalidation_reset(gt);
err = xe_uc_stop(>->uc);
if (err)
@@ -529,6 +528,8 @@ static int gt_reset(struct xe_gt *gt)
if (err)
goto err_out;
+ xe_gt_tlb_invalidation_reset(gt);
+
err = do_gt_restart(gt);
if (err)
goto err_out;
--
2.41.0
next prev parent reply other threads:[~2023-07-10 9:42 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-10 9:40 [Intel-xe] [PATCH v6 00/11] Try to handle TLB invalidations from CT fast-path Matthew Auld
2023-07-10 9:40 ` [Intel-xe] [PATCH v6 01/11] drm/xe/tlb: drop unnecessary smp_wmb() Matthew Auld
2023-07-10 9:40 ` [Intel-xe] [PATCH v6 02/11] drm/xe/tlb: ensure we access seqno_recv once Matthew Auld
2023-07-10 9:40 ` [Intel-xe] [PATCH v6 03/11] drm/xe: hold mem_access.ref for CT fast-path Matthew Auld
2023-07-10 9:40 ` [Intel-xe] [PATCH v6 04/11] drm/xe/ct: hold fast_lock when reserving space for g2h Matthew Auld
2023-07-10 9:40 ` [Intel-xe] [PATCH v6 05/11] drm/xe/tlb: increment next seqno after successful CT send Matthew Auld
2023-07-10 9:40 ` [Intel-xe] [PATCH v6 06/11] drm/xe/ct: serialise fast_lock during CT disable Matthew Auld
2023-07-10 9:40 ` Matthew Auld [this message]
2023-07-10 9:40 ` [Intel-xe] [PATCH v6 08/11] drm/xe/tlb: also update seqno_recv during reset Matthew Auld
2023-07-10 9:40 ` [Intel-xe] [PATCH v6 09/11] drm/xe/tlb: print seqno_recv on fence TLB timeout Matthew Auld
2023-07-10 9:40 ` [Intel-xe] [PATCH v6 10/11] drm/xe/ct: update g2h outstanding for CTB capture Matthew Auld
2023-07-10 13:42 ` Matthew Brost
2023-07-10 9:40 ` [Intel-xe] [PATCH v6 11/11] drm/xe: handle TLB invalidations from CT fast-path Matthew Auld
2023-07-10 10:13 ` [Intel-xe] ✓ CI.Patch_applied: success for Try to handle TLB invalidations from CT fast-path (rev4) Patchwork
2023-07-10 10:13 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork
2023-07-10 10:15 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork
2023-07-10 10:19 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-07-10 10:19 ` [Intel-xe] ✓ CI.Hooks: " Patchwork
2023-07-10 10:20 ` [Intel-xe] ✓ CI.checksparse: " Patchwork
2023-07-10 11:06 ` [Intel-xe] ○ CI.BAT: info " Patchwork
2023-07-10 14:41 ` [Intel-xe] [PATCH v6 00/11] Try to handle TLB invalidations from CT fast-path Souza, Jose
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