From: Matt Roper <matthew.d.roper@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: matthew.d.roper@intel.com
Subject: [Intel-xe] [PATCH 4/4] drm/xe: Stop tracking 4-tile support
Date: Thu, 17 Aug 2023 16:04:12 -0700 [thread overview]
Message-ID: <20230817230407.909816-10-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20230817230407.909816-6-matthew.d.roper@intel.com>
The choice of Y-major tiling format (either the legacy "TileY" or the
newer "Tile4") is based on graphics IP version (12.50 and beyond have
Tile4, earlier platforms have TileY). Only display was using the
has_4tile feature flag, but that handling is now self-contained within
the display code itself, so we no longer need to track this feature flag
in the main Xe driver.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/xe/xe_device_types.h | 2 --
drivers/gpu/drm/xe/xe_pci.c | 10 +---------
2 files changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 303447c093c5..dbb732e14606 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -227,8 +227,6 @@ struct xe_device {
u8 force_execlist:1;
/** @has_flat_ccs: Whether flat CCS metadata is used */
u8 has_flat_ccs:1;
- /** @has_4tile: Whether tile-4 tiling is supported */
- u8 has_4tile:1;
/** @has_llc: Device has a shared CPU+GPU last level cache */
u8 has_llc:1;
/** @has_range_tlb_invalidation: Has range based TLB invalidations */
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 46e3a9632efe..f6bc6ae1c920 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -80,12 +80,6 @@ struct xe_device_desc {
u8 is_dgfx:1;
u8 has_display:1;
- /*
- * FIXME: Xe doesn't care about presence/lack of 4tile since we can
- * already determine that from the graphics IP version. This flag
- * should eventually move entirely into the display code's own logic.
- */
- u8 has_4tile:1;
u8 has_llc:1;
};
@@ -277,8 +271,7 @@ static const u16 dg2_g12_ids[] = { XE_DG2_G12_IDS(NOP), 0 };
{ XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \
{ XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \
{ } \
- }, \
- .has_4tile = 1
+ }
static const struct xe_device_desc ats_m_desc = {
.graphics = &graphics_xehpg,
@@ -555,7 +548,6 @@ static int xe_info_init(struct xe_device *xe,
xe->info.is_dgfx = desc->is_dgfx;
xe->info.graphics_name = graphics_desc->name;
xe->info.media_name = media_desc ? media_desc->name : "none";
- xe->info.has_4tile = desc->has_4tile;
xe->info.has_llc = desc->has_llc;
xe->info.dma_mask_size = graphics_desc->dma_mask_size;
--
2.41.0
next prev parent reply other threads:[~2023-08-17 23:04 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-17 23:04 [Intel-xe] [PATCH 0/4] Stop tracking Tile4 support Matt Roper
2023-08-17 23:04 ` [Intel-xe] [PATCH 1/4] drm/i915/selftest: Simplify Y-major tiling in blit selftest Matt Roper
2023-08-17 23:04 ` [Intel-xe] [PATCH 2/4] drm/i915: Eliminate has_4tile feature flag Matt Roper
2023-08-17 23:04 ` [Intel-xe] [PATCH 3/4] fixup! drm/xe/display: Implement display support Matt Roper
2023-08-18 21:56 ` Lucas De Marchi
2023-08-17 23:04 ` Matt Roper [this message]
2023-08-18 21:56 ` [Intel-xe] [PATCH 4/4] drm/xe: Stop tracking 4-tile support Lucas De Marchi
2023-08-17 23:08 ` [Intel-xe] ✓ CI.Patch_applied: success for Stop tracking Tile4 support Patchwork
2023-08-17 23:08 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork
2023-08-17 23:09 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork
2023-08-17 23:13 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-08-17 23:13 ` [Intel-xe] ✓ CI.Hooks: " Patchwork
2023-08-17 23:14 ` [Intel-xe] ✗ CI.checksparse: warning " Patchwork
2023-08-17 23:41 ` [Intel-xe] ✓ CI.BAT: success " Patchwork
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