From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B9179C678DD for ; Thu, 17 Aug 2023 23:04:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 699B210E239; Thu, 17 Aug 2023 23:04:17 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0FFDD10E254 for ; Thu, 17 Aug 2023 23:04:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1692313456; x=1723849456; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kAtI2Oy3qXIg5t+wZpg8C+4htJ2jmuJo4L+HyWEGZf8=; b=cOBdS/bKqu94npvvTJleIoRVGgUMsVGFe40Nw7qKZMRZ6Ll1UFg7eCOl PfEtCwVYVvD+gOo/VyAT+xHM8flk/mD6GGwA9QCXDvj6OGD28ziQzFW7y CWIB9W208PH85MV6cSTFoHihDXoFKXrOWGBW0vmYTxK6oAV05ySc9i6Kv ny+RCouBwIXS3TWH0pY0tJTW9fq32DNINFDk72pWaUdG+HuwVWBq2zIFd WQByR0fV9LHjkfeBczwvYij8FsqrPUJhPgwnmwlLHM/VMVF9SGfGs1Qxf L+HX8qFyOf4DFZzLDvt9zBOrQ2djcxAjwgLrcE3l28DfceY4F8sOcOqWy w==; X-IronPort-AV: E=McAfee;i="6600,9927,10805"; a="375736159" X-IronPort-AV: E=Sophos;i="6.01,181,1684825200"; d="scan'208";a="375736159" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2023 16:04:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10805"; a="734827899" X-IronPort-AV: E=Sophos;i="6.01,181,1684825200"; d="scan'208";a="734827899" Received: from mdroper-desk1.fm.intel.com ([10.1.27.147]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Aug 2023 16:04:15 -0700 From: Matt Roper To: intel-xe@lists.freedesktop.org Date: Thu, 17 Aug 2023 16:04:09 -0700 Message-ID: <20230817230407.909816-7-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230817230407.909816-6-matthew.d.roper@intel.com> References: <20230817230407.909816-6-matthew.d.roper@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [Intel-xe] [PATCH 1/4] drm/i915/selftest: Simplify Y-major tiling in blit selftest X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: matthew.d.roper@intel.com Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Rather than picking random tiling formats from a pool that contains both TileY and Tile4 and then trying to replace one with the other depending on the platform, it's simpler to just use a single enum value that represents whatever the platform-appropriate Y-major tiling format is (i.e., Tile4 on Xe_HP and beyond, legacy TileY on earlier platforms). Signed-off-by: Matt Roper Reviewed-by: Haridhar Kalvala Link: https://patchwork.freedesktop.org/patch/msgid/20230810234618.3738870-3-matthew.d.roper@intel.com (cherry picked from commit 3d623691ca300676699a56d5ec154ebcbe5d63eb) --- .../i915/gem/selftests/i915_gem_client_blt.c | 39 +++++++------------ 1 file changed, 15 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c index ff81af4c8202..10a7847f1b04 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c @@ -83,8 +83,7 @@ static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp) enum client_tiling { CLIENT_TILING_LINEAR, CLIENT_TILING_X, - CLIENT_TILING_Y, - CLIENT_TILING_4, + CLIENT_TILING_Y, /* Y-major, either Tile4 (Xe_HP and beyond) or legacy TileY */ CLIENT_NUM_TILING_TYPES }; @@ -165,11 +164,10 @@ static int prepare_blit(const struct tiled_blits *t, BLIT_CCTL_DST_MOCS(gt->mocs.uc_index)); src_pitch = t->width; /* in dwords */ - if (src->tiling == CLIENT_TILING_4) { - src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR); - src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4; - } else if (src->tiling == CLIENT_TILING_Y) { + if (src->tiling == CLIENT_TILING_Y) { src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR); + if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 50)) + src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4; } else if (src->tiling == CLIENT_TILING_X) { src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X); } else { @@ -177,11 +175,10 @@ static int prepare_blit(const struct tiled_blits *t, } dst_pitch = t->width; /* in dwords */ - if (dst->tiling == CLIENT_TILING_4) { - dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR); - dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4; - } else if (dst->tiling == CLIENT_TILING_Y) { + if (dst->tiling == CLIENT_TILING_Y) { dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR); + if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 50)) + dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4; } else if (dst->tiling == CLIENT_TILING_X) { dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X); } else { @@ -326,12 +323,6 @@ static int tiled_blits_create_buffers(struct tiled_blits *t, t->buffers[i].vma = vma; t->buffers[i].tiling = i915_prandom_u32_max_state(CLIENT_NUM_TILING_TYPES, prng); - - /* Platforms support either TileY or Tile4, not both */ - if (HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_Y) - t->buffers[i].tiling = CLIENT_TILING_4; - else if (!HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_4) - t->buffers[i].tiling = CLIENT_TILING_Y; } return 0; @@ -367,18 +358,19 @@ static u64 tiled_offset(const struct intel_gt *gt, y = div64_u64_rem(v, stride, &x); - if (tiling == CLIENT_TILING_4) { - v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32); - - /* no swizzling for f-tiling */ - swizzle = I915_BIT_6_SWIZZLE_NONE; - } else if (tiling == CLIENT_TILING_X) { + if (tiling == CLIENT_TILING_X) { v = div64_u64_rem(y, 8, &y) * stride * 8; v += y * 512; v += div64_u64_rem(x, 512, &x) << 12; v += x; swizzle = gt->ggtt->bit_6_swizzle_x; + } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) { + /* Y-major tiling layout is Tile4 for Xe_HP and beyond */ + v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32); + + /* no swizzling for f-tiling */ + swizzle = I915_BIT_6_SWIZZLE_NONE; } else { const unsigned int ytile_span = 16; const unsigned int ytile_height = 512; @@ -414,8 +406,7 @@ static const char *repr_tiling(enum client_tiling tiling) switch (tiling) { case CLIENT_TILING_LINEAR: return "linear"; case CLIENT_TILING_X: return "X"; - case CLIENT_TILING_Y: return "Y"; - case CLIENT_TILING_4: return "F"; + case CLIENT_TILING_Y: return "Y / 4"; default: return "unknown"; } } -- 2.41.0