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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?0TtkFf17XIndjz3dAfu1dm4SvGDUlFkrO/1IenrFv7pblK133krGaUfq8NZh?= =?us-ascii?Q?UYFwr0I0OffNu2rdSY+m7YdTkPUUbCRoeSYiu6ojYYeDPDFbG2pkHBPOnPxl?= =?us-ascii?Q?3hFIeRI+xEJyKnixpMDR2kDOkY5K+84MMlWZPtxn1SrYf4nkELrDU1fi47QW?= =?us-ascii?Q?N7fEbB92RkNlAtUyh/augxuXpvJNoPkKHLafCVujZG3oet8EiA+juO+MLg8d?= =?us-ascii?Q?icLxEWQTQCVRJS/MqUDaJU+EC3v1iWG5rWbekO9Wb79kcXtoB4i4ebsgzQFr?= =?us-ascii?Q?HGV/pl0zUms7H0ghLUQQeqdVwUsSn+/YIuzAFhWk0UqWP4B5ZuP/hr02xMNN?= =?us-ascii?Q?wkeiZ+FwIZaq5dpaAy8Dt40FPQ/+R0wQ2Xc9O00zsF0Z2zpMlUUojZHHlwBu?= =?us-ascii?Q?iYG0fg+wFjy1mTQLkxL9Esb7NOuQ6SkOd/O7ggnHZ0yEjiIadm3WpK4grHXV?= =?us-ascii?Q?4gPkCh6F7Xvz5zW+OScHS+/tznERfXwysgn63XASfbmmRkoAXWvlo6HKvbqt?= =?us-ascii?Q?2gqPBr80qxPnqElMZegir0YKtATOzl0epmBjj2EEYpIkiuhD101GBvQwmQka?= =?us-ascii?Q?pb+19vnL6U6XAJTg+y7NDBm2ZLtk5+tRUkKOrSYiJncnahShu09UT4oAjt2/?= =?us-ascii?Q?5JTCChKISY6j3lwRbvjEtsWkOZxEXQyd1om1ulejIH9po0NfcxdnbHhsFU1w?= =?us-ascii?Q?XGMfFVQlrZNMYTRDPJuN3yoW9oxxPRjHps1y5UUwSh6Q5yofsDg5hDCJAiMu?= =?us-ascii?Q?+CkRkdJ9Ann1F8HyM3fmnnCD2VETYF9CvYy5XM8QDckE7euxREqzMUa3ugEm?= =?us-ascii?Q?wNemLtJ1m7rvSVFdBf3KRGlEL85kxqV1zdOKhkIUIhhap8HLKimUkarxyP0G?= =?us-ascii?Q?ZsG0p82R00v5Yh6pXLFBVSMdA9DudsiyLQimIOnVyBRUm/7JLJuEuOdgIXWf?= =?us-ascii?Q?3HbcrtPiCy6dYH4iHCmC8koaw3MlAZvbSjXh7dMqa23QFMQhlS04hbJwoJnM?= =?us-ascii?Q?e1pjoBPeTWqol0Eqsm5YxVTCjuqtxbPaPBYAoNeUpkYvZu9OfCRZgySjjIid?= =?us-ascii?Q?/UapJLr//gBgj4dL8Q/m+oITIyqNLigeQMo1twm90WLNJ0Hi1J9a8S4KHE82?= =?us-ascii?Q?0vFsojmZuYvoG71/r5KcgoXGXdQXt3hO0I4f3kdQjAoBAxxeHTm1HMCAzNai?= =?us-ascii?Q?3PfaIrhIi+z3JBKtsPQep4QZFpwm8l/y6YdLDbZnkX4QhxngtCAmdLSqQEGe?= =?us-ascii?Q?x7hInnWK301hjMcvj45KHzFSKSpLbaxltMYYzG9NAGw+ebO8MgBLvJToGx4C?= =?us-ascii?Q?3CNTuRM3LEKZOb6S6xOqHLILOUSu3vKttJ8vnIc8GN5HgDX+GszvPbWPqzMx?= =?us-ascii?Q?QYjv71vWQgpJYOZ8MNxKLuGbafVf7VXCDuFREpHlcQEJ5kQgfK8kErKkIlzT?= =?us-ascii?Q?X2GIMuE1Gf+ic3wAh+uziWsAY9ifT0EfHJv/uVy7PCKDntv5YUeIJTGTt2MQ?= =?us-ascii?Q?5SEK/c+heLx5GtcBR3hB/OZ7Vw4gcPoef+AqsTiu6KZ5p4RDBJU1Pk4+GuBo?= =?us-ascii?Q?EaeUMA0uXgeOSOCM1AqGlC8tfXl0poPVkyaWoGuIE6MsUTN/k8V6IJuWZwt/?= =?us-ascii?Q?sg=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: f2966698-08ae-4c20-3051-08dbafbc1039 X-MS-Exchange-CrossTenant-AuthSource: DS7PR11MB7859.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2023 16:04:07.0593 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 03wt9KDkJ9CgZXNg9wZrOyyV+PoKzw9ytLX/u3+bmGAqSyZQMyEBCdzPMEs6OjNWMAUK574f8+kKIEaKHwYMLJCvuWGNzT4O6+nBhiLfklU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR11MB8185 X-OriginatorOrg: intel.com Subject: Re: [Intel-xe] [Intel-gfx] [PATCH v2 01/27] drm/i915/xelpdp: Add XE_LPDP_FEATURES X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Thu, Sep 07, 2023 at 08:37:31AM -0700, Lucas De Marchi wrote: > Add a FEATURES macro for XE_LPD+ as this is expected to be the baseline > for Xe2_LPD and will allow to see the delta more easily. Would it be simpler to do #define XE_LPDP_FEATURES \ XE_LPD_FEATURES \ /* additional deltas */ so that it's more obvious what the deltas between Xe_LPD -> Xe_LPD+ are too? > > Signed-off-by: Lucas De Marchi > --- > .../drm/i915/display/intel_display_device.c | 60 ++++++++++++++++--- > 1 file changed, 52 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c > index c39f8a15d8aa..089674e2f1d2 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_device.c > +++ b/drivers/gpu/drm/i915/display/intel_display_device.c > @@ -710,18 +710,62 @@ static const struct intel_display_device_info xe_hpd_display = { > BIT(PORT_TC1), > }; > > +#define XE_LPDP_FEATURES \ > + .abox_mask = GENMASK(1, 0), \ > + .color = { \ > + .degamma_lut_size = 129, .gamma_lut_size = 1024, \ > + .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \ > + DRM_COLOR_LUT_EQUAL_CHANNELS, \ > + }, \ > + .dbuf.size = 4096, \ > + .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \ > + BIT(DBUF_S4), \ > + .has_cdclk_crawl = 1, \ > + .has_cdclk_squash = 1, \ > + .has_ddi = 1, \ > + .has_dp_mst = 1, \ > + .has_dsb = 1, \ > + .has_fpga_dbg = 1, \ > + .has_hotplug = 1, \ > + .has_ipc = 1, \ > + .has_psr = 1, \ > + .pipe_offsets = { \ > + [TRANSCODER_A] = PIPE_A_OFFSET, \ > + [TRANSCODER_B] = PIPE_B_OFFSET, \ > + [TRANSCODER_C] = PIPE_C_OFFSET, \ > + [TRANSCODER_D] = PIPE_D_OFFSET, \ > + [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ > + [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ If we're expanding out the whole definition rather than defining this as XE_LPD_FEATURES + deltas, then there's no need for the DSI here. > + }, \ > + .trans_offsets = { \ > + [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ > + [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ > + [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ > + [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ > + [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ > + [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ Or here. > + }, \ > + TGL_CURSOR_OFFSETS, \ > + \ > + .__runtime_defaults.cpu_transcoder_mask = \ > + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ > + BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \ > + .__runtime_defaults.ip.ver = 13, \ Xe_LPD+'s ip version is 14 rather than 13. > + .__runtime_defaults.has_dmc = 1, \ > + .__runtime_defaults.has_dsc = 1, \ > + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \ And the FBC is on A + B. Matt > + .__runtime_defaults.has_hdcp = 1, \ > + .__runtime_defaults.pipe_mask = \ > + BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ > + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | \ > + BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4) > + > + > static const struct intel_display_device_info xe_lpdp_display = { > - XE_LPD_FEATURES, > - .has_cdclk_crawl = 1, > - .has_cdclk_squash = 1, > + XE_LPDP_FEATURES, > > .__runtime_defaults.ip.ver = 14, > .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B), > - .__runtime_defaults.cpu_transcoder_mask = > - BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | > - BIT(TRANSCODER_C) | BIT(TRANSCODER_D), > - .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | > - BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), > }; > > /* > -- > 2.40.1 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation