From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C4A07CE7B17 for ; Thu, 28 Sep 2023 10:05:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 78E9E10E601; Thu, 28 Sep 2023 10:05:52 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7A5EE10E601 for ; Thu, 28 Sep 2023 10:05:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695895550; x=1727431550; h=from:to:subject:date:message-id:mime-version: content-transfer-encoding; bh=KHQwXq//7MvB9JpQfmGTtrN+0fxpKPpJu5wM3oXaxwg=; b=UiNC+YUHTN+EKh6DO0su/m5BjQqSd+H0+hneZ1FqR2MiotwoykMoU0h3 OPAyDnZlI2O3uX2ReGEmzoGx3C/KyhRAxfXPRsLdVEXk7J0cu7nufJm4C cIzQK+Nsck9tsOlQ2LjvkHIbovh2fV38XVlMNbGw3w5VNZdQd2rb3gkwW xBjZg1H0ysHtojZaDYdrR3v4GKA2798H5CH2qhythOQoCHpbDm/71mZ+4 sadBRQ8+K1BUIJearuA1+N5CUzLiosUmtM5cRh6c6x0Xf2M46sqkJQBXR aZssQbaKvg2hWWCQtWFNOVnvmZ6kHbGf5y3w2E1yzsw/7+9ZHWDz86vUS g==; X-IronPort-AV: E=McAfee;i="6600,9927,10846"; a="380901682" X-IronPort-AV: E=Sophos;i="6.03,183,1694761200"; d="scan'208";a="380901682" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2023 03:05:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10846"; a="819782237" X-IronPort-AV: E=Sophos;i="6.03,183,1694761200"; d="scan'208";a="819782237" Received: from nlesniak-mobl.ger.corp.intel.com (HELO mwauld-desk1.intel.com) ([10.252.28.108]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2023 03:05:48 -0700 From: Matthew Auld To: intel-xe@lists.freedesktop.org Date: Thu, 28 Sep 2023 11:05:38 +0100 Message-ID: <20230928100537.392675-7-matthew.auld@intel.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Intel-xe] [PATCH v6 0/5] PAT and cache coherency support X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Branch available here: https://gitlab.freedesktop.org/mwa/kernel/-/tree/xe-pat-index?ref_type=heads Goal here is to allow userspace to directly control the pat_index when mapping memory via the ppGTT, in addtion to the CPU caching mode. This is very much needed on newer igpu platforms which allow incoherent GT access, where the choice over the cache level and expected coherency is best left to userspace depending on their usecase. In the future there may also be other stuff encoded in the pat_index, so giving userspace direct control will also be needed there. To support this we added new gem_create uAPI for selecting the CPU cache mode to use for system memory, including the expected GPU coherency mode. There are various restrictions here for the selected coherency mode and compatible CPU cache modes. With that in place the actual pat_index can now be provided as part of vm_bind. The only restriction is that the coherency mode of the pat_index must be at least as coherent as the gem_create coherency mode. There are also some special cases like with userptr and dma-buf. v2: - Loads of improvements/tweaks. Main changes are to now allow gem_create.coh_mode <= coh_mode(pat_index), rather than it needing to match exactly. This simplifies the dma-buf policy from userspace pov. Also we now only consider COH_NONE and COH_AT_LEAST_1WAY. v3: - Rebase. Split the pte_encode() refactoring, plus various smaller tweaks and fixes. v4: - Rebase on Lucas' new series. - Drop UC cache mode. - s/smem_cpu_caching/cpu_caching/. Idea is to make VRAM WC explicit in the uapi, plus make it more future proof. v5: - Rebase, plus some small tweaks and fixes. v6: - CI hooks fixes + checkpatch. -- 2.41.0