From: Riana Tauro <riana.tauro@intel.com>
To: intel-xe@lists.freedesktop.org
Subject: [PATCH v2 1/8] RFC drm/xe: Move user engine class mappings to functions
Date: Thu, 7 Dec 2023 18:27:55 +0530 [thread overview]
Message-ID: <20231207125802.3730165-2-riana.tauro@intel.com> (raw)
In-Reply-To: <20231207125802.3730165-1-riana.tauro@intel.com>
Move user engine class <-> hw engine class arrays to function
calls so that it can be used in different files.
No functional changes.
v2: change array to function
Cc: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Riana Tauro <riana.tauro@intel.com>
---
drivers/gpu/drm/xe/xe_exec_queue.c | 19 ++----------
drivers/gpu/drm/xe/xe_hw_engine.c | 50 ++++++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_hw_engine.h | 3 ++
drivers/gpu/drm/xe/xe_query.c | 23 ++------------
4 files changed, 57 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index 85574740bc1e..86d20be53134 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -482,31 +482,16 @@ static int exec_queue_user_extensions(struct xe_device *xe, struct xe_exec_queue
return 0;
}
-static const enum xe_engine_class user_to_xe_engine_class[] = {
- [DRM_XE_ENGINE_CLASS_RENDER] = XE_ENGINE_CLASS_RENDER,
- [DRM_XE_ENGINE_CLASS_COPY] = XE_ENGINE_CLASS_COPY,
- [DRM_XE_ENGINE_CLASS_VIDEO_DECODE] = XE_ENGINE_CLASS_VIDEO_DECODE,
- [DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE] = XE_ENGINE_CLASS_VIDEO_ENHANCE,
- [DRM_XE_ENGINE_CLASS_COMPUTE] = XE_ENGINE_CLASS_COMPUTE,
-};
-
static struct xe_hw_engine *
find_hw_engine(struct xe_device *xe,
struct drm_xe_engine_class_instance eci)
{
- u32 idx;
-
- if (eci.engine_class > ARRAY_SIZE(user_to_xe_engine_class))
- return NULL;
if (eci.gt_id >= xe->info.gt_count)
return NULL;
- idx = array_index_nospec(eci.engine_class,
- ARRAY_SIZE(user_to_xe_engine_class));
-
return xe_gt_hw_engine(xe_device_get_gt(xe, eci.gt_id),
- user_to_xe_engine_class[idx],
+ xe_hw_engine_from_user_class(eci.engine_class),
eci.engine_instance, true);
}
@@ -532,7 +517,7 @@ static u32 bind_exec_queue_logical_mask(struct xe_device *xe, struct xe_gt *gt,
continue;
if (hwe->class ==
- user_to_xe_engine_class[DRM_XE_ENGINE_CLASS_COPY])
+ xe_hw_engine_from_user_class(DRM_XE_ENGINE_CLASS_COPY))
logical_mask |= BIT(hwe->logical_instance);
}
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index c56e7cec350e..4a13b6fffccb 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -264,6 +264,56 @@ static u32 hw_engine_mmio_read32(struct xe_hw_engine *hwe, struct xe_reg reg)
return xe_mmio_read32(hwe->gt, reg);
}
+/**
+ * xe_hw_engine_to_user_class - converts xe hw engine to user engine class
+ * @engine_class: hw engine class
+ *
+ * Returns: user engine class on success, -1 on error
+ */
+u16 xe_hw_engine_to_user_class(enum xe_engine_class engine_class)
+{
+ switch (engine_class) {
+ case XE_ENGINE_CLASS_RENDER:
+ return DRM_XE_ENGINE_CLASS_RENDER;
+ case XE_ENGINE_CLASS_COPY:
+ return DRM_XE_ENGINE_CLASS_COPY;
+ case XE_ENGINE_CLASS_VIDEO_DECODE:
+ return DRM_XE_ENGINE_CLASS_VIDEO_DECODE;
+ case XE_ENGINE_CLASS_VIDEO_ENHANCE:
+ return DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE;
+ case XE_ENGINE_CLASS_COMPUTE:
+ return DRM_XE_ENGINE_CLASS_COMPUTE;
+ default:
+ XE_WARN_ON(engine_class);
+ return -1;
+ }
+}
+
+/**
+ * xe_hw_engine_from_user_class - converts xe user engine class to hw engine class
+ * @engine_class: user engine class
+ *
+ * Returns: hw engine class on success
+ */
+enum xe_engine_class xe_hw_engine_from_user_class(u16 engine_class)
+{
+ switch (engine_class) {
+ case DRM_XE_ENGINE_CLASS_RENDER:
+ return XE_ENGINE_CLASS_RENDER;
+ case DRM_XE_ENGINE_CLASS_COPY:
+ return XE_ENGINE_CLASS_COPY;
+ case DRM_XE_ENGINE_CLASS_VIDEO_DECODE:
+ return XE_ENGINE_CLASS_VIDEO_DECODE;
+ case DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE:
+ return XE_ENGINE_CLASS_VIDEO_ENHANCE;
+ case DRM_XE_ENGINE_CLASS_COMPUTE:
+ return XE_ENGINE_CLASS_COMPUTE;
+ default:
+ XE_WARN_ON(engine_class);
+ return XE_ENGINE_CLASS_MAX;
+ }
+}
+
void xe_hw_engine_enable_ring(struct xe_hw_engine *hwe)
{
u32 ccs_mask =
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.h b/drivers/gpu/drm/xe/xe_hw_engine.h
index 71968ee2f600..89ca96063644 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.h
+++ b/drivers/gpu/drm/xe/xe_hw_engine.h
@@ -62,6 +62,9 @@ void xe_hw_engine_print(struct xe_hw_engine *hwe, struct drm_printer *p);
void xe_hw_engine_setup_default_lrc_state(struct xe_hw_engine *hwe);
bool xe_hw_engine_is_reserved(struct xe_hw_engine *hwe);
+enum xe_engine_class xe_hw_engine_from_user_class(u16 engine_class);
+u16 xe_hw_engine_to_user_class(enum xe_engine_class engine_class);
+
static inline bool xe_hw_engine_is_valid(struct xe_hw_engine *hwe)
{
return hwe->name;
diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c
index 56d61bf596b2..8b28cc376fff 100644
--- a/drivers/gpu/drm/xe/xe_query.c
+++ b/drivers/gpu/drm/xe/xe_query.c
@@ -22,22 +22,6 @@
#include "xe_mmio.h"
#include "xe_ttm_vram_mgr.h"
-static const u16 xe_to_user_engine_class[] = {
- [XE_ENGINE_CLASS_RENDER] = DRM_XE_ENGINE_CLASS_RENDER,
- [XE_ENGINE_CLASS_COPY] = DRM_XE_ENGINE_CLASS_COPY,
- [XE_ENGINE_CLASS_VIDEO_DECODE] = DRM_XE_ENGINE_CLASS_VIDEO_DECODE,
- [XE_ENGINE_CLASS_VIDEO_ENHANCE] = DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE,
- [XE_ENGINE_CLASS_COMPUTE] = DRM_XE_ENGINE_CLASS_COMPUTE,
-};
-
-static const enum xe_engine_class user_to_xe_engine_class[] = {
- [DRM_XE_ENGINE_CLASS_RENDER] = XE_ENGINE_CLASS_RENDER,
- [DRM_XE_ENGINE_CLASS_COPY] = XE_ENGINE_CLASS_COPY,
- [DRM_XE_ENGINE_CLASS_VIDEO_DECODE] = XE_ENGINE_CLASS_VIDEO_DECODE,
- [DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE] = XE_ENGINE_CLASS_VIDEO_ENHANCE,
- [DRM_XE_ENGINE_CLASS_COMPUTE] = XE_ENGINE_CLASS_COMPUTE,
-};
-
static size_t calc_hw_engine_info_size(struct xe_device *xe)
{
struct xe_hw_engine *hwe;
@@ -139,10 +123,7 @@ query_engine_cycles(struct xe_device *xe,
if (!gt)
return -EINVAL;
- if (eci->engine_class >= ARRAY_SIZE(user_to_xe_engine_class))
- return -EINVAL;
-
- hwe = xe_gt_hw_engine(gt, user_to_xe_engine_class[eci->engine_class],
+ hwe = xe_gt_hw_engine(gt, xe_hw_engine_from_user_class(eci->engine_class),
eci->engine_instance, true);
if (!hwe)
return -EINVAL;
@@ -208,7 +189,7 @@ static int query_engines(struct xe_device *xe,
continue;
engines->engines[i].instance.engine_class =
- xe_to_user_engine_class[hwe->class];
+ xe_hw_engine_to_user_class(hwe->class);
engines->engines[i].instance.engine_instance =
hwe->logical_instance;
engines->engines[i].instance.gt_id = gt->info.id;
--
2.40.0
next prev parent reply other threads:[~2023-12-07 12:50 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-07 12:57 [PATCH v2 0/8] Engine Busyness Riana Tauro
2023-12-07 12:53 ` ✓ CI.Patch_applied: success for Engine Busyness (rev2) Patchwork
2023-12-07 12:53 ` ✗ CI.checkpatch: warning " Patchwork
2023-12-07 12:54 ` ✓ CI.KUnit: success " Patchwork
2023-12-07 12:57 ` Riana Tauro [this message]
2023-12-07 12:57 ` [PATCH v2 2/8] RFC drm/xe/guc: Add interface for engine busyness ticks Riana Tauro
2023-12-21 0:49 ` Umesh Nerlige Ramappa
2023-12-21 5:14 ` Riana Tauro
2023-12-07 12:57 ` [PATCH v2 3/8] RFC drm/xe/guc: Expose engine busyness only for supported GuC version Riana Tauro
2023-12-21 0:52 ` Umesh Nerlige Ramappa
2023-12-21 5:17 ` Riana Tauro
2023-12-07 12:57 ` [PATCH v2 4/8] RFC drm/xe/guc: Add PMU counter for total active ticks Riana Tauro
2023-12-07 12:57 ` [PATCH v2 5/8] RFC drm/xe/uapi: Add configs for Engine busyness Riana Tauro
2023-12-21 2:29 ` Umesh Nerlige Ramappa
2023-12-21 5:26 ` Riana Tauro
2023-12-07 12:58 ` [PATCH v2 6/8] RFC drm/xe/pmu: Add PMU counters for engine busy ticks Riana Tauro
2023-12-07 12:58 ` [PATCH v2 7/8] RFC drm/xe/guc: Dynamically enable/disable engine busyness stats Riana Tauro
2023-12-07 12:58 ` [PATCH v2 8/8] RFC drm/xe/guc: Handle runtime suspend issues for engine busyness Riana Tauro
2023-12-07 13:01 ` ✓ CI.Build: success for Engine Busyness (rev2) Patchwork
2023-12-07 13:02 ` ✓ CI.Hooks: " Patchwork
2023-12-07 13:03 ` ✓ CI.checksparse: " Patchwork
2023-12-07 13:39 ` ✗ CI.BAT: failure " Patchwork
2023-12-07 14:45 ` [PATCH v2 0/8] Engine Busyness Tvrtko Ursulin
2023-12-14 1:56 ` Umesh Nerlige Ramappa
2023-12-14 8:06 ` Tvrtko Ursulin
2023-12-20 5:36 ` Umesh Nerlige Ramappa
2023-12-20 9:00 ` Tvrtko Ursulin
2023-12-20 23:58 ` Umesh Nerlige Ramappa
2023-12-21 9:36 ` Tvrtko Ursulin
2023-12-21 13:17 ` Nerlige Ramappa, Umesh
2023-12-22 9:41 ` Tvrtko Ursulin
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231207125802.3730165-2-riana.tauro@intel.com \
--to=riana.tauro@intel.com \
--cc=intel-xe@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox