From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 770AFC10F1D for ; Fri, 8 Dec 2023 06:43:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4AE1310E9F6; Fri, 8 Dec 2023 06:43:41 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 58AA910E9D6 for ; Fri, 8 Dec 2023 06:43:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1702017817; x=1733553817; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8w9aMvwW7SY2UIvWr0Oboif1ScrJV7Ih+5ljL3YEcEU=; b=YwTx8ff7u4XDf0jmIvkPVIz3paLKDjy792N4Nqe1FBW+p7vmvEDS4woU 8Cml3Te4LXvqhgMa+FDAPSHjODVr1dcZ4G2IE8XQeT3Sxbt+zpo31pdY4 mPUHzSvEHnkcgMWQtUb/j+6r1IFehCfZubkGrTyukRRV9xaLYLb9003MI Eg55hXiwLZ/OhGpbbuhy7DjcKlFGxImS90xkOplOtTtsT8UheOVpVCTMZ 6pPguo6Njzk/r9rHIpTQWDo9Am9f1zr8JueTVNR3rCwKkTOpYTqXO+Uh0 ZsGwy9bDCZHSBR7nWF9YO+MKYevFw228Q+AXRi+bmtgaG2qF0zOu+PLj2 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10917"; a="373866618" X-IronPort-AV: E=Sophos;i="6.04,260,1695711600"; d="scan'208";a="373866618" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2023 22:43:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10917"; a="775699272" X-IronPort-AV: E=Sophos;i="6.04,260,1695711600"; d="scan'208";a="775699272" Received: from orsosgc001.jf.intel.com (HELO unerlige-ril.jf.intel.com) ([10.165.21.138]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Dec 2023 22:43:36 -0800 From: Ashutosh Dixit To: intel-xe@lists.freedesktop.org Subject: [PATCH 17/17] drm/xe/oa: Override GuC RC with OA on PVC Date: Thu, 7 Dec 2023 22:43:29 -0800 Message-ID: <20231208064329.2387604-18-ashutosh.dixit@intel.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231208064329.2387604-1-ashutosh.dixit@intel.com> References: <20231208064329.2387604-1-ashutosh.dixit@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On PVC, a w/a resets RCS/CCS before it goes into RC6. This breaks OA since OA does not expect engine resets during its use. Fix it by disabling RC6. Reviewed-by: Umesh Nerlige Ramappa Signed-off-by: Ashutosh Dixit --- drivers/gpu/drm/xe/xe_guc_pc.c | 60 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/xe/xe_guc_pc.h | 3 ++ drivers/gpu/drm/xe/xe_oa.c | 25 ++++++++++++- drivers/gpu/drm/xe/xe_oa_types.h | 3 ++ 4 files changed, 90 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c index d2605a684b1c5..fb576d1fa8dc3 100644 --- a/drivers/gpu/drm/xe/xe_guc_pc.c +++ b/drivers/gpu/drm/xe/xe_guc_pc.c @@ -228,6 +228,27 @@ static int pc_action_set_param(struct xe_guc_pc *pc, u8 id, u32 value) return ret; } +static int pc_action_unset_param(struct xe_guc_pc *pc, u8 id) +{ + struct xe_guc_ct *ct = &pc_to_guc(pc)->ct; + int ret; + u32 action[] = { + GUC_ACTION_HOST2GUC_PC_SLPC_REQUEST, + SLPC_EVENT(SLPC_EVENT_PARAMETER_UNSET, 1), + id, + }; + + if (wait_for_pc_state(pc, SLPC_GLOBAL_STATE_RUNNING)) + return -EAGAIN; + + ret = xe_guc_ct_send(ct, action, ARRAY_SIZE(action), 0, 0); + if (ret) + drm_err(&pc_to_xe(pc)->drm, "GuC PC unset param failed: %pe", + ERR_PTR(ret)); + + return ret; +} + static int pc_action_setup_gucrc(struct xe_guc_pc *pc, u32 mode) { struct xe_guc_ct *ct = &pc_to_guc(pc)->ct; @@ -818,6 +839,45 @@ int xe_guc_pc_gucrc_disable(struct xe_guc_pc *pc) return ret; } +/** + * xe_guc_pc_override_gucrc_mode() - override GUCRC mode + * @pc: Xe_GuC_PC instance + * @mode: new value of the mode. + * + * Override the GUCRC mode. + * + * Return: 0 on success, negative error code on error. + */ +int xe_guc_pc_override_gucrc_mode(struct xe_guc_pc *pc, enum slpc_gucrc_mode mode) +{ + int ret; + + xe_device_mem_access_get(pc_to_xe(pc)); + ret = pc_action_set_param(pc, SLPC_PARAM_PWRGATE_RC_MODE, mode); + xe_device_mem_access_put(pc_to_xe(pc)); + + return ret; +} + +/** + * xe_guc_pc_override_gucrc_mode() - override GUCRC mode + * @pc: Xe_GuC_PC instance + * + * Unset the GUCRC mode override + * + * Return: 0 on success, negative error code on error. + */ +int xe_guc_pc_unset_gucrc_mode(struct xe_guc_pc *pc) +{ + int ret; + + xe_device_mem_access_get(pc_to_xe(pc)); + ret = pc_action_unset_param(pc, SLPC_PARAM_PWRGATE_RC_MODE); + xe_device_mem_access_put(pc_to_xe(pc)); + + return ret; +} + static void pc_init_pcode_freq(struct xe_guc_pc *pc) { u32 min = DIV_ROUND_CLOSEST(pc->rpn_freq, GT_FREQUENCY_MULTIPLIER); diff --git a/drivers/gpu/drm/xe/xe_guc_pc.h b/drivers/gpu/drm/xe/xe_guc_pc.h index 054788e006f32..51b99c357e048 100644 --- a/drivers/gpu/drm/xe/xe_guc_pc.h +++ b/drivers/gpu/drm/xe/xe_guc_pc.h @@ -7,12 +7,15 @@ #define _XE_GUC_PC_H_ #include "xe_guc_pc_types.h" +#include "abi/guc_actions_slpc_abi.h" int xe_guc_pc_init(struct xe_guc_pc *pc); void xe_guc_pc_fini(struct xe_guc_pc *pc); int xe_guc_pc_start(struct xe_guc_pc *pc); int xe_guc_pc_stop(struct xe_guc_pc *pc); int xe_guc_pc_gucrc_disable(struct xe_guc_pc *pc); +int xe_guc_pc_override_gucrc_mode(struct xe_guc_pc *pc, enum slpc_gucrc_mode mode); +int xe_guc_pc_unset_gucrc_mode(struct xe_guc_pc *pc); enum xe_gt_idle_state xe_guc_pc_c_status(struct xe_guc_pc *pc); u64 xe_guc_pc_rc6_residency(struct xe_guc_pc *pc); diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c index 13c6e516d9169..34b3f16333550 100644 --- a/drivers/gpu/drm/xe/xe_oa.c +++ b/drivers/gpu/drm/xe/xe_oa.c @@ -22,6 +22,7 @@ #include "xe_bo.h" #include "xe_gt.h" #include "xe_gt_mcr.h" +#include "xe_guc_pc.h" #include "xe_lrc.h" #include "xe_mmio.h" #include "xe_oa.h" @@ -901,6 +902,10 @@ static void xe_oa_stream_destroy(struct xe_oa_stream *stream) xe_device_mem_access_put(stream->oa->xe); xe_oa_free_oa_buffer(stream); + /* Wa_1509372804:pvc: Unset the override of GUCRC mode to enable rc6 */ + if (stream->override_gucrc) + XE_WARN_ON(xe_guc_pc_unset_gucrc_mode(>->uc.guc.pc)); + xe_oa_free_configs(stream); } @@ -1384,9 +1389,24 @@ static int xe_oa_stream_init(struct xe_oa_stream *stream, goto exit; } + /* + * Wa_1509372804:pvc + * + * GuC reset of engines causes OA to lose configuration + * state. Prevent this by overriding GUCRC mode. + */ + if (stream->oa->xe->info.platform == XE_PVC) { + ret = xe_guc_pc_override_gucrc_mode(>->uc.guc.pc, + SLPC_GUCRC_MODE_GUCRC_NO_RC6); + if (ret) + goto err_free_configs; + + stream->override_gucrc = true; + } + ret = xe_oa_alloc_oa_buffer(stream); if (ret) - goto err_free_configs; + goto err_unset_gucrc; /* Take runtime pm ref and forcewake to disable RC6 */ xe_device_mem_access_get(stream->oa->xe); @@ -1429,6 +1449,9 @@ static int xe_oa_stream_init(struct xe_oa_stream *stream, XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL)); xe_device_mem_access_put(stream->oa->xe); xe_oa_free_oa_buffer(stream); +err_unset_gucrc: + if (stream->override_gucrc) + XE_WARN_ON(xe_guc_pc_unset_gucrc_mode(>->uc.guc.pc)); err_free_configs: xe_oa_free_configs(stream); exit: diff --git a/drivers/gpu/drm/xe/xe_oa_types.h b/drivers/gpu/drm/xe/xe_oa_types.h index bcd8d249faaec..e11555bac7c79 100644 --- a/drivers/gpu/drm/xe/xe_oa_types.h +++ b/drivers/gpu/drm/xe/xe_oa_types.h @@ -226,5 +226,8 @@ struct xe_oa_stream { /** @poll_period_ns: hrtimer period for checking OA buffer for available data */ u64 poll_period_ns; + + /** @override_gucrc: GuC RC has been overridden for the OA stream */ + bool override_gucrc; }; #endif -- 2.41.0