Re: [PATCH v3 1/1] drm/xe/xe2_lpg: Introduce performance guide changes

[Matt Roper <matthew.d.roper@intel.com>]

On Mon, Jan 22, 2024 at 11:19:04AM +0530, Shekhar Chauhan wrote:
> Add performance guide changes to Xe2_LPG.
> 
> BSpec: 72161
> Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h | 6 ++++++
>  drivers/gpu/drm/xe/xe_tuning.c       | 9 ++++++++-
>  2 files changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 0d4bfc35ff37..cd27480f6486 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -144,6 +144,9 @@
>  
>  #define GSCPSMI_BASE				XE_REG(0x880c)
>  
> +#define CCCHKNREG1				XE_REG_MCR(0x8828)
> +#define   ENCOMPPERFFIX				REG_BIT(18)
> +
>  /* Fuse readout registers for GT */
>  #define XEHP_FUSE4				XE_REG(0x9114)
>  #define   CFEG_WMTP_DISABLE			REG_BIT(20)
> @@ -289,6 +292,9 @@
>  #define XEHP_L3NODEARBCFG			XE_REG_MCR(0xb0b4)
>  #define   XEHP_LNESPARE				REG_BIT(19)
>  
> +#define L3SQCREG3				XE_REG_MCR(0xb108)
> +#define   COMPPWOVERFETCHEN			REG_BIT(28)
> +
>  #define XEHP_L3SQCREG5				XE_REG_MCR(0xb158)
>  #define   L3_PWM_TIMER_INIT_VAL_MASK		REG_GENMASK(9, 0)
>  
> diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
> index 53ccd338fd8c..3ae1c0622c32 100644
> --- a/drivers/gpu/drm/xe/xe_tuning.c
> +++ b/drivers/gpu/drm/xe/xe_tuning.c
> @@ -37,7 +37,14 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>  	  XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
>  				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
>  	},
> -
> +	{ XE_RTP_NAME("Tuning: Compression Overfetch"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2004, XE_RTP_END_VERSION_UNDEFINED)),
> +	  XE_RTP_ACTIONS(SET(CCCHKNREG1, ENCOMPPERFFIX)),

I think you meant to use CLR instead of SET here, right?  Since the
setting we want is the "Disable..." line item, which turns off bit 18
that the hardware already has set by default.


Matt

> +	},
> +	{ XE_RTP_NAME("Tuning: Enable compressible partial write overfetch in L3"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2004, XE_RTP_END_VERSION_UNDEFINED)),
> +	  XE_RTP_ACTIONS(SET(L3SQCREG3, COMPPWOVERFETCHEN))
> +	},
>  	{}
>  };
>  
> -- 
> 2.34.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation