Re: [PATCH 1/1] drm/xe: correct the assertion for number of PTEs

[Matt Roper <matthew.d.roper@intel.com>]

On Wed, Jan 24, 2024 at 10:52:45PM -0800, fei.yang@intel.com wrote:
> From: Fei Yang <fei.yang@intel.com>
> 
> While one MI_STORE_DATA_IMM can take no more than 0x1fe qwords,
> the size of the pgtable can be 512 entries.
> 
> Fixes: 43d48379c939 ("drm/xe: correct the calculation of remaining size")
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Fei Yang <fei.yang@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

and applied to drm-xe-next.  Thanks for the patch.


Matt

> ---
>  drivers/gpu/drm/xe/xe_migrate.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index 7abf15546ced..9ab004871f9a 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -71,6 +71,7 @@ struct xe_migrate {
>  #define NUM_KERNEL_PDE 17
>  #define NUM_PT_SLOTS 32
>  #define LEVEL0_PAGE_TABLE_ENCODE_SIZE SZ_2M
> +#define MAX_NUM_PTE 512
>  
>  /*
>   * Although MI_STORE_DATA_IMM's "length" field is 10-bits, 0x3FE is the largest
> @@ -1107,7 +1108,7 @@ static void write_pgtable(struct xe_tile *tile, struct xe_bb *bb, u64 ppgtt_ofs,
>  	 * This shouldn't be possible in practice.. might change when 16K
>  	 * pages are used. Hence the assert.
>  	 */
> -	xe_tile_assert(tile, update->qwords <= MAX_PTE_PER_SDI);
> +	xe_tile_assert(tile, update->qwords < MAX_NUM_PTE);
>  	if (!ppgtt_ofs)
>  		ppgtt_ofs = xe_migrate_vram_ofs(tile_to_xe(tile),
>  						xe_bo_addr(update->pt_bo, 0,
> -- 
> 2.25.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation