From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A1F9BC48285 for ; Tue, 30 Jan 2024 21:22:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 41F5F10E05A; Tue, 30 Jan 2024 21:22:16 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id AC8E01135D4 for ; Tue, 30 Jan 2024 21:22:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706649735; x=1738185735; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZppdoRLNM4MTmRxvNOzBsOhPQhVH3q6iKwXg2N9/FOw=; b=RE+3fKV7nb0gmDaXOX01nIA7HtG9wSZ95R8Tk01cmcxs9yiWLaxD++37 bTA17Ftskz4PjwozDwib1PfJOzoE4Qsi8OJfNKks0yNyuN5vsXjI5rRBp HO6xRNBCfJXixgOvSgYBs3IRHfFA2UTBdIcciO+qWNjj04GdssgC2pOAl XrlTpLlbCWG3zTt/GiGkJtvWde94kv6OvhHWv4RfhpUDQ6GdiSVSDKylw zPYEN0ZjpXlZ1WKQRDRy83cvjP/DiRiHORcIPX8qAcx1SaOuXx63mI+av 5xv9/u8Qxw1Tq8oMbflW2hVn3viTyeyUFGA/pjzQPzBd1AaEPBMMZL+ca A==; X-IronPort-AV: E=McAfee;i="6600,9927,10969"; a="10504697" X-IronPort-AV: E=Sophos;i="6.05,230,1701158400"; d="scan'208";a="10504697" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jan 2024 13:22:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10969"; a="788327371" X-IronPort-AV: E=Sophos;i="6.05,230,1701158400"; d="scan'208";a="788327371" Received: from guc-pnp-dev-box-1.fm.intel.com ([10.1.27.7]) by orsmga002.jf.intel.com with ESMTP; 30 Jan 2024 13:22:14 -0800 From: Zhanjun Dong To: intel-xe@lists.freedesktop.org Subject: [PATCH v5 1/1] drm/xe: Expose number of dss per group and helpers Date: Tue, 30 Jan 2024 13:22:08 -0800 Message-Id: <20240130212208.235448-2-zhanjun.dong@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240130212208.235448-1-zhanjun.dong@intel.com> References: <20240130212208.235448-1-zhanjun.dong@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Expose helper for dss per group. This is a precursor patch to allow for easier iteration through MCR registers and other per-DSS uses. Signed-off-by: Zhanjun Dong --- drivers/gpu/drm/xe/xe_gt_mcr.c | 40 ++++++++++++++++++++++++++++- drivers/gpu/drm/xe/xe_gt_mcr.h | 17 ++++++++++++ drivers/gpu/drm/xe/xe_gt_topology.c | 3 --- drivers/gpu/drm/xe/xe_gt_types.h | 2 ++ 4 files changed, 58 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c index 77925b35cf8d..ad2e42dc2218 100644 --- a/drivers/gpu/drm/xe/xe_gt_mcr.c +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c @@ -291,11 +291,16 @@ static void init_steering_mslice(struct xe_gt *gt) gt->steering[LNCF].instance_target = 0; /* unused */ } +int xe_gt_mcr_get_dss_per_group(struct xe_gt *gt) +{ + return gt_to_xe(gt)->info.platform == XE_PVC ? 8 : 4; +} + static void init_steering_dss(struct xe_gt *gt) { unsigned int dss = min(xe_dss_mask_group_ffs(gt->fuse_topo.g_dss_mask, 0, 0), xe_dss_mask_group_ffs(gt->fuse_topo.c_dss_mask, 0, 0)); - unsigned int dss_per_grp = gt_to_xe(gt)->info.platform == XE_PVC ? 8 : 4; + unsigned int dss_per_grp = xe_gt_mcr_get_dss_per_group(gt); gt->steering[DSS].group_target = dss / dss_per_grp; gt->steering[DSS].instance_target = dss % dss_per_grp; @@ -683,3 +688,36 @@ void xe_gt_mcr_steering_dump(struct xe_gt *gt, struct drm_printer *p) } } } + +/** + * xe_gt_mcr_get_dss_steering - returns the group/instance steering for a DSS + * @gt: GT structure + * @dss: DSS ID to obtain steering for + * @group: pointer to storage for steering group ID + * @instance: pointer to storage for steering instance ID + * + * Returns the steering IDs (via the @group and @instance parameters) that + * correspond to a specific DSS ID. + */ +void xe_gt_mcr_get_dss_steering(struct xe_gt *gt, unsigned int dss, unsigned int *group, + unsigned int *instance) +{ + int dss_per_grp = xe_gt_mcr_get_dss_per_group(gt); + + *group = dss / dss_per_grp; + *instance = dss % dss_per_grp; +} + +bool xe_gt_mcr_dss_has_subslice(struct xe_gt *gt, int slice, int subslice) +{ + int dss_per_grp = xe_gt_mcr_get_dss_per_group(gt); + int index = slice * dss_per_grp + subslice; + + if (index >= XE_MAX_DSS_FUSE_BITS) { + xe_gt_dbg(gt, "DSS id out of range: slice:%d subslice:%d\n", slice, subslice); + return false; + } + + return test_bit(index, gt->fuse_topo.g_dss_mask) || + test_bit(index, gt->fuse_topo.c_dss_mask); +} diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.h b/drivers/gpu/drm/xe/xe_gt_mcr.h index 27ca1bc880a0..356f21978eb8 100644 --- a/drivers/gpu/drm/xe/xe_gt_mcr.h +++ b/drivers/gpu/drm/xe/xe_gt_mcr.h @@ -7,6 +7,7 @@ #define _XE_GT_MCR_H_ #include "regs/xe_reg_defs.h" +#include "xe_gt_types.h" struct drm_printer; struct xe_gt; @@ -25,5 +26,21 @@ void xe_gt_mcr_multicast_write(struct xe_gt *gt, struct xe_reg_mcr mcr_reg, u32 value); void xe_gt_mcr_steering_dump(struct xe_gt *gt, struct drm_printer *p); +int xe_gt_mcr_get_dss_per_group(struct xe_gt *gt); +void xe_gt_mcr_get_dss_steering(struct xe_gt *gt, unsigned int dss, unsigned int *group, + unsigned int *instance); +bool xe_gt_mcr_dss_has_subslice(struct xe_gt *gt, int slice, int subslice); + +#define _HAS_DSS(gt__, group__, instance__) xe_gt_mcr_dss_has_subslice(gt__, group__, instance__) + +/* + * Loop over each subslice/DSS and determine the group and instance IDs that + * should be used to steer MCR accesses toward this DSS. + */ +#define for_each_dss_steering(dss_, gt_, group_, instance_) \ + for (dss_ = 0, xe_gt_mcr_get_dss_steering(gt_, 0, &(group_), &(instance_)); \ + dss_ < XE_MAX_DSS_FUSE_BITS; \ + dss_++, xe_gt_mcr_get_dss_steering(gt_, dss_, &(group_), &(instance_))) \ + for_each_if(_HAS_DSS(gt_, (group_), (instance_))) #endif /* _XE_GT_MCR_H_ */ diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c index a8d7f272c30a..e973eeaac7f1 100644 --- a/drivers/gpu/drm/xe/xe_gt_topology.c +++ b/drivers/gpu/drm/xe/xe_gt_topology.c @@ -11,9 +11,6 @@ #include "xe_gt.h" #include "xe_mmio.h" -#define XE_MAX_DSS_FUSE_BITS (32 * XE_MAX_DSS_FUSE_REGS) -#define XE_MAX_EU_FUSE_BITS (32 * XE_MAX_EU_FUSE_REGS) - static void load_dss_mask(struct xe_gt *gt, xe_dss_mask_t mask, int numregs, ...) { diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h index 70c615dd1498..b926606edb38 100644 --- a/drivers/gpu/drm/xe/xe_gt_types.h +++ b/drivers/gpu/drm/xe/xe_gt_types.h @@ -25,7 +25,9 @@ enum xe_gt_type { }; #define XE_MAX_DSS_FUSE_REGS 3 +#define XE_MAX_DSS_FUSE_BITS (32 * XE_MAX_DSS_FUSE_REGS) #define XE_MAX_EU_FUSE_REGS 1 +#define XE_MAX_EU_FUSE_BITS (32 * XE_MAX_EU_FUSE_REGS) typedef unsigned long xe_dss_mask_t[BITS_TO_LONGS(32 * XE_MAX_DSS_FUSE_REGS)]; typedef unsigned long xe_eu_mask_t[BITS_TO_LONGS(32 * XE_MAX_EU_FUSE_REGS)]; -- 2.34.1