From: Matthew Auld <matthew.auld@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: Nirmoy Das <nirmoy.das@intel.com>
Subject: [PATCH 1/3] drm/xe/queue: fix engine_class bounds check
Date: Mon, 18 Mar 2024 18:05:33 +0000 [thread overview]
Message-ID: <20240318180532.57522-4-matthew.auld@intel.com> (raw)
The engine_class is the index into the user_to_xe_engine_class,
therefore it needs to be less than.
Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Nirmoy Das <nirmoy.das@intel.com>
---
drivers/gpu/drm/xe/xe_exec_queue.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index 6a83bc57826a..2016c1af9633 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -440,7 +440,7 @@ find_hw_engine(struct xe_device *xe,
{
u32 idx;
- if (eci.engine_class > ARRAY_SIZE(user_to_xe_engine_class))
+ if (eci.engine_class >= ARRAY_SIZE(user_to_xe_engine_class))
return NULL;
if (eci.gt_id >= xe->info.gt_count)
--
2.44.0
next reply other threads:[~2024-03-18 18:05 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-03-18 18:05 Matthew Auld [this message]
2024-03-18 18:05 ` [PATCH 2/3] drm/xe/device: fix XE_MAX_GT_PER_TILE check Matthew Auld
2024-03-18 18:42 ` Nirmoy Das
2024-03-18 18:05 ` [PATCH 3/3] drm/xe/device: fix XE_MAX_TILES_PER_DEVICE check Matthew Auld
2024-03-18 18:42 ` [PATCH 1/3] drm/xe/queue: fix engine_class bounds check Nirmoy Das
2024-03-19 1:00 ` ✓ CI.Patch_applied: success for series starting with [1/3] " Patchwork
2024-03-19 1:00 ` ✓ CI.checkpatch: " Patchwork
2024-03-19 1:01 ` ✓ CI.KUnit: " Patchwork
2024-03-19 1:12 ` ✓ CI.Build: " Patchwork
2024-03-19 1:14 ` ✓ CI.Hooks: " Patchwork
2024-03-19 1:15 ` ✓ CI.checksparse: " Patchwork
2024-03-19 1:42 ` ✓ CI.BAT: " Patchwork
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