From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AA3B1C54E64 for ; Mon, 25 Mar 2024 19:07:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 570AD10EAD8; Mon, 25 Mar 2024 19:07:09 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="loOk+YRc"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1A65A10EACF for ; Mon, 25 Mar 2024 19:07:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1711393621; x=1742929621; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bPEcOrTEMull5GlPFvq1mquprI2P9JFht2wSkb95u0M=; b=loOk+YRcPNQvDr5eaAX+tuLzfkNOLKB/+HZdpeHa5LS8VEab8XMoSFi4 s+30yVFp3gvm1YMyhLFpLnptcRp8xYj3HSlBUau5u02g/iNB1tLIa3LBI OE5EgJ950HydY3+rs1Fh0bTcmkawsRI4XMBnZ+d5udhtTBHLRpfcgL94w 8R6sip49RZLnv/ucZmVhqlKXmY1zc22425oLIK1AGjuI77aueOTizMKzy OP8iD6WURy1MkeSLVbykxfhiCl0p5qp5U28jFnlxHLMzPCPUZYEdA6N5+ 0NKJRKXOYu1d91i1uhmbZXfxZFf0HvuQtO8w+UKmp4RfryhIZ4QBqrHUW w==; X-IronPort-AV: E=McAfee;i="6600,9927,11024"; a="6310313" X-IronPort-AV: E=Sophos;i="6.07,154,1708416000"; d="scan'208";a="6310313" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2024 12:06:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,154,1708416000"; d="scan'208";a="20441806" Received: from josouza-mobl2.bz.intel.com ([10.87.243.88]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2024 12:06:55 -0700 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= To: intel-xe@lists.freedesktop.org Cc: Rodrigo Vivi , Matt Roper , Zhanjun Dong , =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= Subject: [PATCH 2/3] drm/xe: Add helpers to loop over geometry and compute DSS Date: Mon, 25 Mar 2024 12:06:42 -0700 Message-ID: <20240325190643.150648-2-jose.souza@intel.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20240325190643.150648-1-jose.souza@intel.com> References: <20240325190643.150648-1-jose.souza@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Some DSS can only be available for geometry while others can only be available for compute. So here adding helpers to loop only available DSS for given usage. User of this helper will come in the next patch. Cc: Rodrigo Vivi Cc: Matt Roper Cc: Zhanjun Dong Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/xe/xe_gt_mcr.h | 24 ++++++++++++++++++++++++ drivers/gpu/drm/xe/xe_gt_topology.c | 17 +++++++++++++++++ drivers/gpu/drm/xe/xe_gt_topology.h | 3 +++ 3 files changed, 44 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.h b/drivers/gpu/drm/xe/xe_gt_mcr.h index a7f4ab1aa584b..e7d03e001a49f 100644 --- a/drivers/gpu/drm/xe/xe_gt_mcr.h +++ b/drivers/gpu/drm/xe/xe_gt_mcr.h @@ -40,4 +40,28 @@ void xe_gt_mcr_get_dss_steering(struct xe_gt *gt, unsigned int dss, u16 *group, for_each_dss((dss), (gt)) \ for_each_if((xe_gt_mcr_get_dss_steering((gt), (dss), &(group), &(instance)), true)) +/* + * Loop over each DSS available for geometry and determine the group and + * instance IDs that should be used to steer MCR accesses toward this DSS. + * @dss: DSS ID to obtain steering for + * @gt: GT structure + * @group: steering group ID, data type: u16 + * @instance: steering instance ID, data type: u16 + */ +#define for_each_geometry_dss(dss, gt, group, instance) \ + for_each_dss_steering(dss, gt, group, instance) \ + if (xe_gt_has_geometry_dss(gt, dss)) + +/* + * Loop over each DSS available for compute and determine the group and + * instance IDs that should be used to steer MCR accesses toward this DSS. + * @dss: DSS ID to obtain steering for + * @gt: GT structure + * @group: steering group ID, data type: u16 + * @instance: steering instance ID, data type: u16 + */ +#define for_each_compute_dss(dss, gt, group, instance) \ + for_each_dss_steering(dss, gt, group, instance) \ + if (xe_gt_has_compute_dss(gt, dss)) + #endif /* _XE_GT_MCR_H_ */ diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c index f5773a14f3c8e..569026cce66af 100644 --- a/drivers/gpu/drm/xe/xe_gt_topology.c +++ b/drivers/gpu/drm/xe/xe_gt_topology.c @@ -166,3 +166,20 @@ bool xe_gt_topology_has_dss_in_quadrant(struct xe_gt *gt, int quad) return quad_first < (quad + 1) * dss_per_quad; } + +static bool has_dss(xe_dss_mask_t dss_mask, unsigned int dss) +{ + unsigned long value = bitmap_get_value8(dss_mask, (dss / 8) * 8); + + return value & BIT(dss % 8); +} + +bool xe_gt_has_geometry_dss(struct xe_gt *gt, unsigned int dss) +{ + return has_dss(gt->fuse_topo.g_dss_mask, dss); +} + +bool xe_gt_has_compute_dss(struct xe_gt *gt, unsigned int dss) +{ + return has_dss(gt->fuse_topo.c_dss_mask, dss); +} diff --git a/drivers/gpu/drm/xe/xe_gt_topology.h b/drivers/gpu/drm/xe/xe_gt_topology.h index b3e357777a6e7..746b325bbf6e4 100644 --- a/drivers/gpu/drm/xe/xe_gt_topology.h +++ b/drivers/gpu/drm/xe/xe_gt_topology.h @@ -33,4 +33,7 @@ bool xe_dss_mask_empty(const xe_dss_mask_t mask); bool xe_gt_topology_has_dss_in_quadrant(struct xe_gt *gt, int quad); +bool xe_gt_has_geometry_dss(struct xe_gt *gt, unsigned int dss); +bool xe_gt_has_compute_dss(struct xe_gt *gt, unsigned int dss); + #endif /* _XE_GT_TOPOLOGY_H_ */ -- 2.44.0