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List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Tue, Apr 02, 2024 at 06:17:22PM +0530, Balasubramani Vivekanandan wrote: > From: Haridhar Kalvala > > Add the initial set of Xe2_HPG gt/engine/lrc workarounds. > > Signed-off-by: Haridhar Kalvala > Signed-off-by: Clint Taylor > Signed-off-by: Gustavo Sousa > Signed-off-by: Dnyaneshar Bhadane > Signed-off-by: Shekhar Chauhan > Signed-off-by: Balasubramani Vivekanandan > --- > drivers/gpu/drm/xe/regs/xe_gt_regs.h | 5 +++ > drivers/gpu/drm/xe/xe_reg_whitelist.c | 4 ++ > drivers/gpu/drm/xe/xe_wa.c | 63 +++++++++++++++++++++++++++ > 3 files changed, 72 insertions(+) > > diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h > index ea75c1f0ebd0..17cc9b6c9536 100644 > --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h > +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h > @@ -74,6 +74,9 @@ > #define WM_CHICKEN3 XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED) > #define HIZ_PLANE_COMPRESSION_DIS REG_BIT(10) > > +#define CHICKEN_RASTER_1 XE_REG_MCR(0x6204, XE_REG_OPTION_MASKED) > +#define DIS_SF_ROUND_NEAREST_EVEN REG_BIT(8) > + > #define CHICKEN_RASTER_2 XE_REG_MCR(0x6208, XE_REG_OPTION_MASKED) > #define TBIMR_FAST_CLIP REG_BIT(5) > > @@ -354,6 +357,7 @@ > #define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2) > > #define ROW_CHICKEN3 XE_REG_MCR(0xe49c, XE_REG_OPTION_MASKED) > +#define XE2_EUPEND_CHK_FLUSH_DIS REG_BIT(14) > #define DIS_FIX_EOT1_FLUSH REG_BIT(9) > > #define TDL_TSL_CHICKEN XE_REG_MCR(0xe4c4, XE_REG_OPTION_MASKED) > @@ -384,6 +388,7 @@ > > #define LSC_CHICKEN_BIT_0 XE_REG_MCR(0xe7c8) > #define DISABLE_D8_D16_COASLESCE REG_BIT(30) > +#define WR_REQ_CHAINING_DIS REG_BIT(26) > #define TGM_WRITE_EOM_FORCE REG_BIT(17) > #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15) > #define SEQUENTIAL_ACCESS_UPGRADE_DISABLE REG_BIT(13) > diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c > index 3fa2ece7d228..e674c8ad230e 100644 > --- a/drivers/gpu/drm/xe/xe_reg_whitelist.c > +++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c > @@ -63,6 +63,10 @@ static const struct xe_rtp_entry_sr register_whitelist[] = { > ENGINE_CLASS(RENDER)), > XE_RTP_ACTIONS(WHITELIST(CSBE_DEBUG_STATUS(RENDER_RING_BASE), 0)) > }, > + { XE_RTP_NAME("16020183090"), > + XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), > + XE_RTP_ACTIONS(WHITELIST(CSBE_DEBUG_STATUS(RENDER_RING_BASE), 0)) > + }, It doesn't look like this workaround applies to Xe2_HPG anymore according to the latest workaround database. The rest of the workarounds look correct, so after dropping this entry, Reviewed-by: Matt Roper Matt > > {} > }; > diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c > index 74b33a3845f2..a163a764d25e 100644 > --- a/drivers/gpu/drm/xe/xe_wa.c > +++ b/drivers/gpu/drm/xe/xe_wa.c > @@ -459,6 +459,55 @@ static const struct xe_rtp_entry_sr engine_was[] = { > XE_RTP_RULES(GRAPHICS_VERSION(2004), FUNC(xe_rtp_match_first_render_or_compute)), > XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, SLM_WMTP_RESTORE)) > }, > + > + /* Xe2_HPG */ > + > + { XE_RTP_NAME("16018712365"), > + XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)), > + XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, XE2_ALLOC_DPA_STARVE_FIX_DIS)) > + }, > + { XE_RTP_NAME("16018737384"), > + XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)), > + XE_RTP_ACTIONS(SET(ROW_CHICKEN, EARLY_EOT_DIS)) > + }, > + { XE_RTP_NAME("14019988906"), > + XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)), > + XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD)) > + }, > + { XE_RTP_NAME("14019877138"), > + XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)), > + XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT)) > + }, > + { XE_RTP_NAME("14020338487"), > + XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)), > + XE_RTP_ACTIONS(SET(ROW_CHICKEN3, XE2_EUPEND_CHK_FLUSH_DIS)) > + }, > + { XE_RTP_NAME("18032247524"), > + XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)), > + XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, SEQUENTIAL_ACCESS_UPGRADE_DISABLE)) > + }, > + { XE_RTP_NAME("14018471104"), > + XE_RTP_RULES(GRAPHICS_VERSION(2001), FUNC(xe_rtp_match_first_render_or_compute)), > + XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, ENABLE_SMP_LD_RENDER_SURFACE_CONTROL)) > + }, > + /* > + * Although this workaround isn't required for the RCS, disabling these > + * reports has no impact for our driver or the GuC, so we go ahead and > + * apply this to all engines for simplicity. > + */ > + { XE_RTP_NAME("16021639441"), > + XE_RTP_RULES(GRAPHICS_VERSION(2001)), > + XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), > + GHWSP_CSB_REPORT_DIS | > + PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS, > + XE_RTP_ACTION_FLAG(ENGINE_BASE))) > + }, > + { XE_RTP_NAME("14019811474"), > + XE_RTP_RULES(GRAPHICS_VERSION(2001), > + FUNC(xe_rtp_match_first_render_or_compute)), > + XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS)) > + }, > + > {} > }; > > @@ -580,6 +629,20 @@ static const struct xe_rtp_entry_sr lrc_was[] = { > XE_RTP_ACTIONS(SET(INSTPM(RENDER_RING_BASE), ENABLE_SEMAPHORE_POLL_BIT)) > }, > > + /* Xe2_HPG */ > + { XE_RTP_NAME("15010599737"), > + XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), > + XE_RTP_ACTIONS(SET(CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN)) > + }, > + { XE_RTP_NAME("14019386621"), > + XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), > + XE_RTP_ACTIONS(SET(VF_SCRATCHPAD, XE2_VFG_TED_CREDIT_INTERFACE_DISABLE)) > + }, > + { XE_RTP_NAME("14020756599"), > + XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)), > + XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS)) > + }, > + > {} > }; > > -- > 2.25.1 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation