From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB1E6C10F15 for ; Thu, 25 Apr 2024 22:38:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 496EC10ECEC; Thu, 25 Apr 2024 22:38:56 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="nk943Ou3"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3851210ECEA for ; Thu, 25 Apr 2024 22:38:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1714084732; x=1745620732; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UNd2+Q88MTqGyd0N5l4YafgY5ulN4YCcLCS1ibqVdo0=; b=nk943Ou36GAB6lKi0wDPdMcO2bk/W+azOGCrUWBn6KZ+hZbDaEkArJQ8 V2JjU/Z4tWiKGovkC6cQs2taqK8ZCRlnxBWgNrcKz5mtmwAlKSw4aaLxs Pz5Ij225hiCd8HccoB1f/X2l3iuVYgXEV6yp2sUyM+7eeODNLTCNPnl6o E4y4nuCL6LA0Mtd6eBgMBZwkZqj2WBV6B3FdyYPNf8QteDpHAl+wFLHBJ LF6vyjLD2dpWihS3jDJrySVQ7HhmpCiEvrOdYrEBP9r19KZ+0iWsqQyw5 NT1vtmg3+WcnvDFhy1HT2aV/yxvDqLcA7wnpOBa1GGgr8j7w7pU4iYglw w==; X-CSE-ConnectionGUID: Cmg6vQSySbichNv5mFDzIQ== X-CSE-MsgGUID: wdv7SHVuQgizgCAoZrIrqQ== X-IronPort-AV: E=McAfee;i="6600,9927,11055"; a="27325063" X-IronPort-AV: E=Sophos;i="6.07,230,1708416000"; d="scan'208";a="27325063" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2024 15:38:52 -0700 X-CSE-ConnectionGUID: 48A580jiSYa/ZU7jR3U4wg== X-CSE-MsgGUID: 7a5UlaosRCWTfQGf90yKnQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,230,1708416000"; d="scan'208";a="56167331" Received: from nirmoyda-desk.igk.intel.com ([10.102.138.190]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Apr 2024 15:38:51 -0700 From: Nirmoy Das To: intel-xe@lists.freedesktop.org Cc: Nirmoy Das Subject: [PATCH v4 5/5] drm/xe: Refactor default device atomic settings Date: Fri, 26 Apr 2024 00:23:46 +0200 Message-ID: <20240425222346.13026-6-nirmoy.das@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240425222346.13026-1-nirmoy.das@intel.com> References: <20240425222346.13026-1-nirmoy.das@intel.com> MIME-Version: 1.0 Organization: Intel Deutschland GmbH, Registered Address: Am Campeon 10, 85579 Neubiberg, Germany, Commercial Register: Amtsgericht Muenchen HRB 186928 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" The default behavior of device atomics depends on the VM type and buffer allocation types. Device atomics are expected to function with all types of allocations for traditional applications/APIs. Additionally, in compute/SVM API scenarios with fault mode or LR mode VMs, device atomics must work with single-region allocations. In all other cases device atomics should be disabled by default. Signed-off-by: Nirmoy Das --- drivers/gpu/drm/xe/xe_pt.c | 24 ++++++++++++++++++++---- drivers/gpu/drm/xe/xe_vm.c | 3 ++- 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c index 5b7930f46cf3..a8e9e8592c43 100644 --- a/drivers/gpu/drm/xe/xe_pt.c +++ b/drivers/gpu/drm/xe/xe_pt.c @@ -597,7 +597,6 @@ static int xe_pt_stage_bind(struct xe_tile *tile, struct xe_vma *vma, struct xe_vm_pgtable_update *entries, u32 *num_entries) { - struct xe_device *xe = tile_to_xe(tile); struct xe_bo *bo = xe_vma_bo(vma); bool is_devmem = !xe_vma_is_userptr(vma) && bo && (xe_bo_is_vram(bo) || xe_bo_is_stolen_devmem(bo)); @@ -619,9 +618,26 @@ xe_pt_stage_bind(struct xe_tile *tile, struct xe_vma *vma, struct xe_pt *pt = xe_vma_vm(vma)->pt_root[tile->id]; int ret; - if ((vma->gpuva.flags & XE_VMA_ATOMIC_PTE_BIT) && - (is_devmem || !IS_DGFX(xe))) - xe_walk.default_pte |= XE_USM_PPGTT_PTE_AE; + /** + * Default atomic expectations for different allocation scenarios are as follows: + * + * 1. Traditional API: When the VM is not in fault mode or LR mode: + * - Device atomics are expected to function with all allocations. + * + * 2. Compute/SVM API: When the VM is either in fault mode or LR mode: + * - Device atomics are the default behavior when the bo is placed in a single region. + * - In all other cases device atomics will be disabled with AE=0 until an application + * request differently using a ioctl like madvise. + */ + if (vma->gpuva.flags & XE_VMA_ATOMIC_PTE_BIT) { + if (xe_vm_in_fault_mode(xe_vma_vm(vma)) || + xe_vm_in_lr_mode(xe_vma_vm(vma))) { + if (bo && xe_bo_has_single_placement(bo)) + xe_walk.default_pte |= XE_USM_PPGTT_PTE_AE; + } else { + xe_walk.default_pte |= XE_USM_PPGTT_PTE_AE; + } + } if (is_devmem) { xe_walk.default_pte |= XE_PPGTT_PTE_DM; diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c index e41345c1627d..ac08b6fd537e 100644 --- a/drivers/gpu/drm/xe/xe_vm.c +++ b/drivers/gpu/drm/xe/xe_vm.c @@ -805,7 +805,8 @@ static struct xe_vma *xe_vma_create(struct xe_vm *vm, for_each_tile(tile, vm->xe, id) vma->tile_mask |= 0x1 << id; - if (GRAPHICS_VER(vm->xe) >= 20 || vm->xe->info.platform == XE_PVC) + if (vm->xe->info.has_atomic_enable_pte_bit && + vm->xe->info.has_device_atomics_on_smem) vma->gpuva.flags |= XE_VMA_ATOMIC_PTE_BIT; vma->pat_index = pat_index; -- 2.42.0