From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: intel-xe@lists.freedesktop.org,
Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>,
Clint Taylor <Clinton.A.Taylor@intel.com>,
Gustavo Sousa <gustavo.sousa@intel.com>,
Jani Nikula <jani.nikula@linux.intel.com>,
Lucas De Marchi <lucas.demarchi@intel.com>,
Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Subject: [PATCH v3 06/19] drm/i915/xe2hpd: Add new C20 PHY SRAM address
Date: Tue, 30 Apr 2024 10:28:37 -0700 [thread overview]
Message-ID: <20240430172850.1881525-7-radhakrishna.sripada@intel.com> (raw)
In-Reply-To: <20240430172850.1881525-1-radhakrishna.sripada@intel.com>
From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Xe2_HPD has different offsets for C20 PHY SRAM configuration context
location. Use the display version to select the right address.
Note that Xe2_LPD uses the same C20 SRAM offsets used by Xe_LPDP (i.e.
MTL's display). According to the BSpec, currently, only Xe2_HPD has
different offsets, so make sure it is the only display using them in the
driver.
v2:
* Redesigned how the right offsets are selected for different display
IP versions.
v3: Fix white space error(RK)
Bspec: 67610
Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 65 ++++++++++++-------
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 48 +++++++++++---
2 files changed, 81 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 2fee024d642b..866b943311f1 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2161,6 +2161,7 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
bool cntx;
intel_wakeref_t wakeref;
int i;
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
wakeref = intel_cx0_phy_transaction_begin(encoder);
@@ -2170,42 +2171,50 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
/* Read Tx configuration */
for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
if (cntx)
- pll_state->tx[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_TX_CNTX_CFG(i));
+ pll_state->tx[i] = intel_c20_sram_read(encoder,
+ INTEL_CX0_LANE0,
+ PHY_C20_B_TX_CNTX_CFG(i915, i));
else
- pll_state->tx[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_TX_CNTX_CFG(i));
+ pll_state->tx[i] = intel_c20_sram_read(encoder,
+ INTEL_CX0_LANE0,
+ PHY_C20_A_TX_CNTX_CFG(i915, i));
}
/* Read common configuration */
for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
if (cntx)
- pll_state->cmn[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_CMN_CNTX_CFG(i));
+ pll_state->cmn[i] = intel_c20_sram_read(encoder,
+ INTEL_CX0_LANE0,
+ PHY_C20_B_CMN_CNTX_CFG(i915, i));
else
- pll_state->cmn[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_CMN_CNTX_CFG(i));
+ pll_state->cmn[i] = intel_c20_sram_read(encoder,
+ INTEL_CX0_LANE0,
+ PHY_C20_A_CMN_CNTX_CFG(i915, i));
}
if (intel_c20phy_use_mpllb(pll_state)) {
/* MPLLB configuration */
for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
if (cntx)
- pll_state->mpllb[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_MPLLB_CNTX_CFG(i));
+ pll_state->mpllb[i] = intel_c20_sram_read(encoder,
+ INTEL_CX0_LANE0,
+ PHY_C20_B_MPLLB_CNTX_CFG(i915, i));
else
- pll_state->mpllb[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_MPLLB_CNTX_CFG(i));
+ pll_state->mpllb[i] = intel_c20_sram_read(encoder,
+ INTEL_CX0_LANE0,
+ PHY_C20_A_MPLLB_CNTX_CFG(i915, i));
}
} else {
/* MPLLA configuration */
for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
if (cntx)
- pll_state->mplla[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_MPLLA_CNTX_CFG(i));
+ pll_state->mplla[i] = intel_c20_sram_read(encoder,
+ INTEL_CX0_LANE0,
+ PHY_C20_B_MPLLA_CNTX_CFG(i915, i));
else
- pll_state->mplla[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_MPLLA_CNTX_CFG(i));
+ pll_state->mplla[i] = intel_c20_sram_read(encoder,
+ INTEL_CX0_LANE0,
+ PHY_C20_A_MPLLA_CNTX_CFG(i915, i));
}
}
@@ -2363,17 +2372,25 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
/* 3.1 Tx configuration */
for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
if (cntx)
- intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_A_TX_CNTX_CFG(i), pll_state->tx[i]);
+ intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
+ PHY_C20_A_TX_CNTX_CFG(i915, i),
+ pll_state->tx[i]);
else
- intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_B_TX_CNTX_CFG(i), pll_state->tx[i]);
+ intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
+ PHY_C20_B_TX_CNTX_CFG(i915, i),
+ pll_state->tx[i]);
}
/* 3.2 common configuration */
for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
if (cntx)
- intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_A_CMN_CNTX_CFG(i), pll_state->cmn[i]);
+ intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
+ PHY_C20_A_CMN_CNTX_CFG(i915, i),
+ pll_state->cmn[i]);
else
- intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_B_CMN_CNTX_CFG(i), pll_state->cmn[i]);
+ intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
+ PHY_C20_B_CMN_CNTX_CFG(i915, i),
+ pll_state->cmn[i]);
}
/* 3.3 mpllb or mplla configuration */
@@ -2381,22 +2398,22 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
if (cntx)
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_MPLLB_CNTX_CFG(i),
+ PHY_C20_A_MPLLB_CNTX_CFG(i915, i),
pll_state->mpllb[i]);
else
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_MPLLB_CNTX_CFG(i),
+ PHY_C20_B_MPLLB_CNTX_CFG(i915, i),
pll_state->mpllb[i]);
}
} else {
for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
if (cntx)
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_MPLLA_CNTX_CFG(i),
+ PHY_C20_A_MPLLA_CNTX_CFG(i915, i),
pll_state->mplla[i]);
else
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_MPLLA_CNTX_CFG(i),
+ PHY_C20_B_MPLLA_CNTX_CFG(i915, i),
pll_state->mplla[i]);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index bdd0c8c4ef97..ab3ae110b68f 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -254,18 +254,50 @@
#define PHY_C20_VDR_CUSTOM_WIDTH 0xD02
#define PHY_C20_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0)
#define PHY_C20_CUSTOM_WIDTH(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val)
-#define PHY_C20_A_TX_CNTX_CFG(idx) (0xCF2E - (idx))
-#define PHY_C20_B_TX_CNTX_CFG(idx) (0xCF2A - (idx))
+
+#define _MTL_C20_A_TX_CNTX_CFG 0xCF2E
+#define _MTL_C20_B_TX_CNTX_CFG 0xCF2A
+#define _MTL_C20_A_CMN_CNTX_CFG 0xCDAA
+#define _MTL_C20_B_CMN_CNTX_CFG 0xCDA5
+#define _MTL_C20_A_MPLLA_CFG 0xCCF0
+#define _MTL_C20_B_MPLLA_CFG 0xCCE5
+#define _MTL_C20_A_MPLLB_CFG 0xCB5A
+#define _MTL_C20_B_MPLLB_CFG 0xCB4E
+
+#define _XE2HPD_C20_A_TX_CNTX_CFG 0xCF5E
+#define _XE2HPD_C20_B_TX_CNTX_CFG 0xCF5A
+#define _XE2HPD_C20_A_CMN_CNTX_CFG 0xCE8E
+#define _XE2HPD_C20_B_CMN_CNTX_CFG 0xCE89
+#define _XE2HPD_C20_A_MPLLA_CFG 0xCE58
+#define _XE2HPD_C20_B_MPLLA_CFG 0xCE4D
+#define _XE2HPD_C20_A_MPLLB_CFG 0xCCC2
+#define _XE2HPD_C20_B_MPLLB_CFG 0xCCB6
+
+#define _IS_XE2HPD_C20(i915) (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
+
+#define PHY_C20_A_TX_CNTX_CFG(i915, idx) \
+ ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_TX_CNTX_CFG : _MTL_C20_A_TX_CNTX_CFG) - (idx))
+#define PHY_C20_B_TX_CNTX_CFG(i915, idx) \
+ ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_TX_CNTX_CFG : _MTL_C20_B_TX_CNTX_CFG) - (idx))
#define C20_PHY_TX_RATE REG_GENMASK(2, 0)
-#define PHY_C20_A_CMN_CNTX_CFG(idx) (0xCDAA - (idx))
-#define PHY_C20_B_CMN_CNTX_CFG(idx) (0xCDA5 - (idx))
-#define PHY_C20_A_MPLLA_CNTX_CFG(idx) (0xCCF0 - (idx))
-#define PHY_C20_B_MPLLA_CNTX_CFG(idx) (0xCCE5 - (idx))
+
+#define PHY_C20_A_CMN_CNTX_CFG(i915, idx) \
+ ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_CMN_CNTX_CFG : _MTL_C20_A_CMN_CNTX_CFG) - (idx))
+#define PHY_C20_B_CMN_CNTX_CFG(i915, idx) \
+ ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_CMN_CNTX_CFG : _MTL_C20_B_CMN_CNTX_CFG) - (idx))
+#define PHY_C20_A_MPLLA_CNTX_CFG(i915, idx) \
+ ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_MPLLA_CFG : _MTL_C20_A_MPLLA_CFG) - (idx))
+#define PHY_C20_B_MPLLA_CNTX_CFG(i915, idx) \
+ ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_MPLLA_CFG : _MTL_C20_B_MPLLA_CFG) - (idx))
#define C20_MPLLA_FRACEN REG_BIT(14)
#define C20_FB_CLK_DIV4_EN REG_BIT(13)
#define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8)
-#define PHY_C20_A_MPLLB_CNTX_CFG(idx) (0xCB5A - (idx))
-#define PHY_C20_B_MPLLB_CNTX_CFG(idx) (0xCB4E - (idx))
+
+#define PHY_C20_A_MPLLB_CNTX_CFG(i915, idx) \
+ ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_MPLLB_CFG : _MTL_C20_A_MPLLB_CFG) - (idx))
+#define PHY_C20_B_MPLLB_CNTX_CFG(i915, idx) \
+ ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_MPLLB_CFG : _MTL_C20_B_MPLLB_CFG) - (idx))
+
#define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13)
#define C20_MPLLB_FRACEN REG_BIT(13)
#define C20_REF_CLK_MPLLB_DIV_MASK REG_GENMASK(12, 10)
--
2.34.1
next prev parent reply other threads:[~2024-04-30 17:30 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-30 17:28 [PATCH v3 00/19] Enable display support for Battlemage Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 01/19] drm/i915/bmg: Lane reversal requires writes to both context lanes Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 02/19] drm/i915/bmg: Define IS_BATTLEMAGE macro Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 03/19] drm/i915/xe2hpd: Initial cdclk table Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 04/19] drm/i915/bmg: Extend DG2 tc check to future Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 05/19] drm/i915/xe2hpd: Properly disable power in port A Radhakrishna Sripada
2024-04-30 17:28 ` Radhakrishna Sripada [this message]
2024-05-03 3:24 ` [PATCH v3 06/19] drm/i915/xe2hpd: Add new C20 PHY SRAM address Sripada, Radhakrishna
2024-04-30 17:28 ` [PATCH v3 07/19] drm/i915/xe2hpd: Add support for eDP PLL configuration Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 08/19] drm/i915/xe2hpd: update pll values in sync with Bspec Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 09/19] drm/i915/xe2hpd: Add display info Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 10/19] drm/i915/xe2hpd: Configure CHICKEN_MISC_2 before enabling planes Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 11/19] drm/i915/xe2hpd: Add max memory bandwidth algorithm Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 12/19] drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 13/19] drm/i915/bmg: BMG should re-use MTL's south display logic Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 14/19] Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping" Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 15/19] drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5 Radhakrishna Sripada
2024-04-30 17:28 ` [PATCH v3 16/19] drm/xe/gt_print: add xe_gt_err_once() Radhakrishna Sripada
2024-05-03 18:34 ` Lucas De Marchi
2024-04-30 17:28 ` [PATCH v3 17/19] drm/xe/device: implement transient flush Radhakrishna Sripada
2024-05-03 18:40 ` Lucas De Marchi
2024-04-30 17:28 ` [PATCH v3 18/19] drm/i915/display: perform " Radhakrishna Sripada
2024-04-30 17:57 ` Lucas De Marchi
2024-04-30 17:28 ` [PATCH v3 19/19] drm/xe/bmg: Enable the display support Radhakrishna Sripada
2024-04-30 17:49 ` Lucas De Marchi
2024-04-30 20:40 ` ✓ CI.Patch_applied: success for Enable display support for Battlemage (rev3) Patchwork
2024-04-30 20:40 ` ✗ CI.checkpatch: warning " Patchwork
2024-04-30 20:41 ` ✓ CI.KUnit: success " Patchwork
2024-04-30 20:53 ` ✓ CI.Build: " Patchwork
2024-04-30 20:55 ` ✓ CI.Hooks: " Patchwork
2024-04-30 20:57 ` ✗ CI.checksparse: warning " Patchwork
2024-05-01 3:04 ` ✗ CI.FULL: failure " Patchwork
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