From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1E725C3DA7F for ; Fri, 19 Jul 2024 20:29:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DE47B10ECB5; Fri, 19 Jul 2024 20:29:25 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Q4M62BpI"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) by gabe.freedesktop.org (Postfix) with ESMTPS id C88B810E16A for ; Fri, 19 Jul 2024 20:29:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721420960; x=1752956960; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1v+yybNxHgIbDdUNifZqpw7CJpHQn3lGfx5cCRgJUNU=; b=Q4M62BpITHRBF0R+62M2I3n3lc3t64GfNUoPHjg50r2v45qayuknoU3G 20hH+dmpQvf/Pc2eL0F2nHVEHzE5RB9QvQ5Ul3ApIWVo57BjTBPvljJbR QBVysP6V7hC/YMT7fxSM3HvF+MXXiF0FF+Bm3HMeXRgWHRxXWMO1A0FvS FL3Ta/5LA4bC75nzbvCoxClOb9SHHVcH/dlemN30VtvXn3OeeWb7zHQse GjMoPVqRhqYrOnEtkc1/ovbsSVIBh09iH3DhAQ9OLQcbUxBsXBvgW+wai 76riKa95lL5r7OXRARxHnmTcgy8PWryqti2VGyV/rKk3hhwXHpKaNibwK Q==; X-CSE-ConnectionGUID: nSthp2FHRqCbwZ4gjt2f1Q== X-CSE-MsgGUID: ZI4p9/FgTiaqIbdfj9JSiw== X-IronPort-AV: E=McAfee;i="6700,10204,11138"; a="18926123" X-IronPort-AV: E=Sophos;i="6.09,221,1716274800"; d="scan'208";a="18926123" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jul 2024 13:29:19 -0700 X-CSE-ConnectionGUID: AuS8qhqISIeTocCqNQVDHQ== X-CSE-MsgGUID: lvJ31G7DTdCKNCWYE/rStg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,221,1716274800"; d="scan'208";a="55412817" Received: from guc-pnp-dev-box-1.fm.intel.com ([10.1.27.7]) by fmviesa003.fm.intel.com with ESMTP; 19 Jul 2024 13:29:19 -0700 From: Zhanjun Dong To: intel-xe@lists.freedesktop.org Cc: Zhanjun Dong , Alan Previn Subject: [PATCH v13 2/5] drm/xe/guc: Add XE_LP steered register lists Date: Fri, 19 Jul 2024 13:29:14 -0700 Message-Id: <20240719202917.1590984-3-zhanjun.dong@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240719202917.1590984-1-zhanjun.dong@intel.com> References: <20240719202917.1590984-1-zhanjun.dong@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Add the ability for runtime allocation and freeing of steered register list extentions that depend on the detected HW config fuses. Signed-off-by: Zhanjun Dong Reviewed-by: Alan Previn --- drivers/gpu/drm/xe/xe_guc_capture.c | 159 +++++++++++++++++++++- drivers/gpu/drm/xe/xe_guc_capture_types.h | 2 + 2 files changed, 159 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_guc_capture.c b/drivers/gpu/drm/xe/xe_guc_capture.c index f520c5fe0363..bf11cd2aaf25 100644 --- a/drivers/gpu/drm/xe/xe_guc_capture.c +++ b/drivers/gpu/drm/xe/xe_guc_capture.c @@ -106,6 +106,7 @@ static const struct __guc_mmio_reg_descr empty_regs_list[] = { TO_GCAP_DEF_OWNER(regsowner), \ TO_GCAP_DEF_TYPE(regstype), \ class, \ + NULL, \ } /* List of lists */ @@ -147,6 +148,11 @@ struct __guc_capture_ads_cache { struct xe_guc_state_capture { const struct __guc_mmio_reg_descr_group *reglists; + /** + * NOTE: steered registers have multiple instances depending on the HW configuration + * (slices or dual-sub-slices) and thus depends on HW fuses discovered + */ + struct __guc_mmio_reg_descr_group *extlists; struct __guc_capture_ads_cache ads_cache[GUC_CAPTURE_LIST_INDEX_MAX] [GUC_STATE_CAPTURE_TYPE_MAX] [GUC_CAPTURE_LIST_CLASS_MAX]; @@ -172,9 +178,137 @@ guc_capture_get_one_list(const struct __guc_mmio_reg_descr_group *reglists, return NULL; } +static struct __guc_mmio_reg_descr_group * +guc_capture_get_one_ext_list(struct __guc_mmio_reg_descr_group *reglists, + u32 owner, u32 type, u32 id) +{ + int i; + + if (!reglists) + return NULL; + + for (i = 0; reglists[i].extlist; ++i) { + if (reglists[i].owner == owner && reglists[i].type == type && + (reglists[i].engine == id || reglists[i].type == GUC_STATE_CAPTURE_TYPE_GLOBAL)) + return ®lists[i]; + } + + return NULL; +} + +struct __ext_steer_reg { + const char *name; + struct xe_reg_mcr reg; +}; + +static const struct __ext_steer_reg xe_extregs[] = { + {"SAMPLER_INSTDONE", SAMPLER_INSTDONE}, + {"ROW_INSTDONE", ROW_INSTDONE} +}; + +static const struct __ext_steer_reg xehpg_extregs[] = { + {"XEHPG_INSTDONE_GEOM_SVGUNIT", XEHPG_INSTDONE_GEOM_SVGUNIT} +}; + +static void __fill_ext_reg(struct __guc_mmio_reg_descr *ext, + const struct __ext_steer_reg *extlist, + int slice_id, int subslice_id) +{ + ext->reg = XE_REG(extlist->reg.__reg.addr); + ext->flags = FIELD_PREP(GUC_REGSET_STEERING_GROUP, slice_id); + ext->flags |= FIELD_PREP(GUC_REGSET_STEERING_INSTANCE, subslice_id); +} + +static int +__alloc_ext_regs(struct drm_device *drm, struct __guc_mmio_reg_descr_group *newlist, + const struct __guc_mmio_reg_descr_group *rootlist, int num_regs) +{ + struct __guc_mmio_reg_descr *list; + + list = drmm_kzalloc(drm, num_regs * sizeof(struct __guc_mmio_reg_descr), GFP_KERNEL); + if (!list) + return -ENOMEM; + + newlist->extlist = list; + newlist->num_regs = num_regs; + newlist->owner = rootlist->owner; + newlist->engine = rootlist->engine; + newlist->type = rootlist->type; + + return 0; +} + +static void +guc_capture_alloc_steered_lists(struct xe_guc *guc, const struct __guc_mmio_reg_descr_group *lists) +{ + struct xe_gt *gt = guc_to_gt(guc); + u16 slice, subslice; + int iter, i, num_steer_regs, num_tot_regs = 0; + const struct __guc_mmio_reg_descr_group *list; + struct __guc_mmio_reg_descr_group *extlists; + struct __guc_mmio_reg_descr *extarray; + bool has_xehpg_extregs; + struct drm_device *drm = >_to_xe(gt)->drm; + + /* steered registers currently only exist for the render-class */ + list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF, + GUC_STATE_CAPTURE_TYPE_ENGINE_CLASS, + GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE); + /* skip if extlists was previously allocated */ + if (!list || guc->capture->extlists) + return; + + has_xehpg_extregs = GRAPHICS_VERx100(gt_to_xe(gt)) >= 1255; + + num_steer_regs = ARRAY_SIZE(xe_extregs); + if (has_xehpg_extregs) + num_steer_regs += ARRAY_SIZE(xehpg_extregs); + + num_tot_regs = num_steer_regs * bitmap_weight(gt->fuse_topo.g_dss_mask, + sizeof(gt->fuse_topo.g_dss_mask) * 8); + if (!num_tot_regs) + return; + + /* allocate an extra for an end marker */ + extlists = drmm_kzalloc(drm, 2 * sizeof(struct __guc_mmio_reg_descr_group), GFP_KERNEL); + if (!extlists) + return; + + if (__alloc_ext_regs(drm, &extlists[0], list, num_tot_regs)) { + drmm_kfree(drm, extlists); + return; + } + + extarray = extlists[0].extlist; + for_each_dss_steering(iter, gt, slice, subslice) { + for (i = 0; i < ARRAY_SIZE(xe_extregs); ++i) { + __fill_ext_reg(extarray, &xe_extregs[i], slice, subslice); + ++extarray; + } + + if (has_xehpg_extregs) { + for (i = 0; i < ARRAY_SIZE(xehpg_extregs); ++i) { + __fill_ext_reg(extarray, &xehpg_extregs[i], slice, subslice); + ++extarray; + } + } + } + + xe_gt_dbg(guc_to_gt(guc), "capture found %d ext-regs.\n", num_tot_regs); + guc->capture->extlists = extlists; +} + static const struct __guc_mmio_reg_descr_group * guc_capture_get_device_reglist(struct xe_guc *guc) { + /* + * For certain engine classes, there are slice and subslice + * level registers requiring steering. We allocate and populate + * these at init time based on hw config add it as an extension + * list at the end of the pre-populated render list. + */ + guc_capture_alloc_steered_lists(guc, xe_lp_lists); + return xe_lp_lists; } @@ -183,9 +317,11 @@ guc_capture_list_init(struct xe_guc *guc, u32 owner, u32 type, enum guc_capture_list_class_type capture_class, struct guc_mmio_reg *ptr, u16 num_entries) { - u32 i = 0; + u32 i = 0, j = 0; const struct __guc_mmio_reg_descr_group *reglists = guc->capture->reglists; + struct __guc_mmio_reg_descr_group *extlists = guc->capture->extlists; const struct __guc_mmio_reg_descr_group *match; + struct __guc_mmio_reg_descr_group *matchext; if (!reglists) return -ENODEV; @@ -201,6 +337,17 @@ guc_capture_list_init(struct xe_guc *guc, u32 owner, u32 type, ptr[i].mask = match->list[i].mask; } + matchext = guc_capture_get_one_ext_list(extlists, owner, type, capture_class); + if (matchext) { + for (i = match->num_regs, j = 0; i < num_entries && + i < (match->num_regs + matchext->num_regs) && + j < matchext->num_regs; ++i, ++j) { + ptr[i].offset = matchext->extlist[j].reg.addr; + ptr[i].value = 0xDEADF00D; + ptr[i].flags = matchext->extlist[j].flags; + ptr[i].mask = matchext->extlist[j].mask; + } + } if (i < num_entries) xe_gt_dbg(guc_to_gt(guc), "Got short capture reglist init: %d out %d.\n", i, num_entries); @@ -213,12 +360,20 @@ guc_cap_list_num_regs(struct xe_guc_state_capture *gc, u32 owner, u32 type, enum guc_capture_list_class_type capture_class) { const struct __guc_mmio_reg_descr_group *match; + struct __guc_mmio_reg_descr_group *matchext; + int num_regs; match = guc_capture_get_one_list(gc->reglists, owner, type, capture_class); if (!match) return 0; - return match->num_regs; + num_regs = match->num_regs; + + matchext = guc_capture_get_one_ext_list(gc->extlists, owner, type, capture_class); + if (matchext) + num_regs += matchext->num_regs; + + return num_regs; } static int diff --git a/drivers/gpu/drm/xe/xe_guc_capture_types.h b/drivers/gpu/drm/xe/xe_guc_capture_types.h index 839148c9fa0f..63cb4d7cf518 100644 --- a/drivers/gpu/drm/xe/xe_guc_capture_types.h +++ b/drivers/gpu/drm/xe/xe_guc_capture_types.h @@ -50,6 +50,8 @@ struct __guc_mmio_reg_descr_group { u32 type; /* see enum guc_state_capture_type */ /** @engine: The engine class */ u32 engine; /* see enum guc_capture_list_class_type */ + /** @extlist: the list for steered registers */ + struct __guc_mmio_reg_descr *extlist; }; #endif -- 2.34.1