From: Ilia Levi <ilia.levi@intel.com>
To: intel-xe@lists.freedesktop.org
Cc: ilia.levi@intel.com, dliberman@habana.ai,
niranjana.vishwanathapura@intel.com, michal.wajdeczko@intel.com
Subject: [PATCH v4 10/11] drm/xe/irq: add default msix
Date: Thu, 25 Jul 2024 13:22:12 +0300 [thread overview]
Message-ID: <20240725102213.2182896-11-ilia.levi@intel.com> (raw)
In-Reply-To: <20240725102213.2182896-1-ilia.levi@intel.com>
From: Dani Liberman <dliberman@habana.ai>
Just like any resource, msix interrupts are limited. To support irq
requests for more than the available number of msix interrupts, we
need a default irq. Once all msix interrupts are allocated, and
allocator returns an error, it is possible to request the default
irq.
We currently set default msix to be used for all exec queues -
requesting unique msix via uapi will be exposed in a later patch.
In particular, lrc priming during probe is done with default msix.
Signed-off-by: Dani Liberman <dliberman@habana.ai>
---
drivers/gpu/drm/xe/xe_device_types.h | 7 +++++
drivers/gpu/drm/xe/xe_exec_queue.c | 11 ++++++--
drivers/gpu/drm/xe/xe_irq.c | 42 ++++++++++++++++++++++++++++
3 files changed, 57 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index d798ce90f8fd..f4db95fe0579 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -321,6 +321,13 @@ struct xe_device {
u16 num_of_interrupts;
/** @irq.msix.indexes: used to allocate msix indexes */
struct xarray indexes;
+ /**
+ * @irq.msix.default_msix: default MSIX to use.
+ *
+ * This is used when not asking for unique MSIX or when all indexes
+ * are already allocated.
+ */
+ u16 default_msix;
} msix;
} irq;
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index c519db7a7a6e..75dcf7f4f125 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -34,7 +34,7 @@ enum xe_exec_queue_sched_prop {
static int exec_queue_user_extensions(struct xe_device *xe, struct xe_exec_queue *q,
u64 extensions, int ext_number);
-static int xe_exec_queue_msix_init(struct xe_device *xe, struct xe_exec_queue *q)
+static int xe_exec_queue_msix_init(struct xe_device *xe, struct xe_exec_queue *q, bool unique_msix)
{
u16 msix;
int ret = 0;
@@ -42,6 +42,11 @@ static int xe_exec_queue_msix_init(struct xe_device *xe, struct xe_exec_queue *q
if (!xe_device_has_msix(xe))
return 0;
+ if (!unique_msix) {
+ q->msix_number = xe->irq.msix.default_msix;
+ return 0;
+ }
+
ret = xe_irq_request_irq(xe, xe_irq_msix_hwe_handler, q->hwe, q->hwe->name, true, &msix);
if (ret < 0) {
drm_dbg(&xe->drm, "Can't allocate unique MSIX to exec queue (%d)\n", ret);
@@ -60,7 +65,7 @@ static void xe_exec_queue_msix_fini(struct xe_exec_queue *q)
if (!xe_device_has_msix(xe))
return;
- if (q->msix_number)
+ if (q->msix_number && q->msix_number != xe->irq.msix.default_msix)
xe_irq_free_irq(xe, q->msix_number);
}
@@ -118,7 +123,7 @@ static struct xe_exec_queue *__xe_exec_queue_alloc(struct xe_device *xe,
else
q->sched_props.priority = XE_EXEC_QUEUE_PRIORITY_NORMAL;
- err = xe_exec_queue_msix_init(xe, q);
+ err = xe_exec_queue_msix_init(xe, q, false);
if (err) {
kfree(q);
return ERR_PTR(err);
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 208d961919ea..1585b7f00170 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -31,6 +31,8 @@
#define IER(offset) XE_REG(offset + 0xc)
enum static_msix_allocations {
+ DEFAULT_MSIX,
+ /* Must be last */
NUM_OF_STATIC_MSIX,
};
@@ -739,8 +741,48 @@ static int xe_irq_msi_request(struct xe_device *xe)
return 0;
}
+static irqreturn_t xe_irq_default_msix_hwe_handler(int irq, void *arg)
+{
+ unsigned int tile_id, gt_id;
+ struct xe_device *xe = arg;
+ struct xe_memirq *memirq;
+ struct xe_hw_engine *hwe;
+ enum xe_hw_engine_id id;
+ struct xe_tile *tile;
+ struct xe_gt *gt;
+
+ for_each_tile(tile, xe, tile_id) {
+ memirq = &tile->memirq;
+ if (!memirq->bo)
+ continue;
+
+ for_each_gt(gt, xe, gt_id) {
+ if (gt->tile != tile)
+ continue;
+
+ for_each_hw_engine(hwe, gt, id)
+ xe_memirq_hwe_handler(memirq, hwe);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
static int xe_irq_msix_request(struct xe_device *xe)
{
+ u16 msix;
+ int err;
+
+ msix = DEFAULT_MSIX;
+ err = xe_irq_request_irq(xe, xe_irq_default_msix_hwe_handler, xe,
+ "default_irq", false, &msix);
+ if (err) {
+ drm_err(&xe->drm, "Failed to request MSIX IRQ %d\n", err);
+ return err;
+ }
+
+ xe->irq.msix.default_msix = DEFAULT_MSIX;
+
return 0;
}
--
2.43.2
next prev parent reply other threads:[~2024-07-25 10:23 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-25 10:22 [PATCH v4 00/11] Add MSIX functionality to XE Ilia Levi
2024-07-25 10:22 ` [PATCH v4 01/11] drm/xe/irq: refactor irq flows to support also msix Ilia Levi
2024-07-25 10:22 ` [PATCH v4 02/11] drm/xe/irq: add msix allocator Ilia Levi
2024-07-25 10:22 ` [PATCH v4 03/11] drm/xe: add irq offset of engine instance 0 to hw engine properties Ilia Levi
2024-07-25 10:22 ` [PATCH v4 04/11] drm/xe: move memirq out of vf Ilia Levi
2024-07-25 10:22 ` [PATCH v4 05/11] drm/xe: memirq infra changes for msix Ilia Levi
2024-07-25 10:22 ` [PATCH v4 06/11] drm/xe/irq: add hw engine irq handler Ilia Levi
2024-07-25 10:22 ` [PATCH v4 07/11] drm/xe: move the kernel lrc from hwe to execlist port Ilia Levi
2024-07-25 10:22 ` [PATCH v4 08/11] drm/xe: msix support preparations - enable memirq Ilia Levi
2024-07-25 10:22 ` [PATCH v4 09/11] drm/xe/exec: adding msix infra to exec queue Ilia Levi
2024-07-25 10:22 ` Ilia Levi [this message]
2024-07-25 10:22 ` [PATCH v4 11/11] drm/xe: msix support for hw engines Ilia Levi
2024-07-25 10:29 ` ✓ CI.Patch_applied: success for Add MSIX functionality to XE (rev6) Patchwork
2024-07-25 10:29 ` ✓ CI.checkpatch: " Patchwork
2024-07-25 10:30 ` ✓ CI.KUnit: " Patchwork
2024-07-25 10:50 ` ✓ CI.Build: " Patchwork
2024-07-25 10:52 ` ✓ CI.Hooks: " Patchwork
2024-07-25 10:53 ` ✓ CI.checksparse: " Patchwork
2024-07-25 11:39 ` ✗ CI.BAT: failure " Patchwork
2024-07-25 13:35 ` ✗ CI.FULL: " Patchwork
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