[PATCH] drm/xe/oa: Insert wmb/sfence before enabling OA

[Ashutosh Dixit <ashutosh.dixit@intel.com>]

In some simulation environments, we occasionally see warnings such as "OAG
Buffer register is not programmed (has value 0). Register offset db08".
This means OA has been enabled before it has been fully configured. Or, the
register write enabling OA has overtaken previous OA configuration register
writes.

Therefore, insert a wmb/sfence to preserve OA register write ordering
before enabling OA.

Reported-by: Guy Zadicario <guy.zadicario@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 drivers/gpu/drm/xe/xe_oa.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_oa.c b/drivers/gpu/drm/xe/xe_oa.c
index 4d4541e0b24c0..02a6baa3c37d9 100644
--- a/drivers/gpu/drm/xe/xe_oa.c
+++ b/drivers/gpu/drm/xe/xe_oa.c
@@ -440,6 +440,9 @@ static void xe_oa_enable(struct xe_oa_stream *stream)
 	val = __format_to_oactrl(format, regs->oa_ctrl_counter_select_mask) |
 		__oa_ccs_select(stream) | OAG_OACONTROL_OA_COUNTER_ENABLE;
 
+	/* Flush previous writes to HW before enabling OA */
+	wmb();
+
 	xe_mmio_write32(stream->gt, regs->oa_ctrl, val);
 }
 
-- 
2.41.0