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From: Matt Roper <matthew.d.roper@intel.com>
To: Matt Atwood <matthew.s.atwood@intel.com>
Cc: <intel-xe@lists.freedesktop.org>,
	Gustavo Sousa <gustavo.sousa@intel.com>
Subject: Re: [PATCH 4/9] drm/xe/xe3: Add initial set of workarounds
Date: Wed, 11 Sep 2024 11:03:33 -0700	[thread overview]
Message-ID: <20240911180333.GF5774@mdroper-desk1.amr.corp.intel.com> (raw)
In-Reply-To: <20240906215153.31210-5-matthew.s.atwood@intel.com>

On Fri, Sep 06, 2024 at 02:51:48PM -0700, Matt Atwood wrote:
> From: Gustavo Sousa <gustavo.sousa@intel.com>
> 
> Implement the initial set of workarounds for Xe3 IPs.
> 
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_engine_regs.h |  1 +
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h     |  3 ++
>  drivers/gpu/drm/xe/xe_wa.c               | 46 ++++++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_wa_oob.rules       |  1 +
>  4 files changed, 51 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> index 81b71903675e..7c78496e6213 100644
> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> @@ -186,6 +186,7 @@
>  
>  #define VDBOX_CGCTL3F10(base)			XE_REG((base) + 0x3f10)
>  #define   IECPUNIT_CLKGATE_DIS			REG_BIT(22)
> +#define   RAMDFTUNIT_CLKGATE_DIS		REG_BIT(9)
>  
>  #define VDBOX_CGCTL3F18(base)			XE_REG((base) + 0x3f18)
>  #define   ALNUNIT_CLKGATE_DIS			REG_BIT(13)
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 8ed855b31e95..259221d2f217 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -286,6 +286,9 @@
>  #define   GAMTLBVEBOX0_CLKGATE_DIS		REG_BIT(16)
>  #define   LTCDD_CLKGATE_DIS			REG_BIT(10)
>  
> +#define UNSLCGCTL9454				XE_REG(0x9454)
> +#define   LSCFE_CLKGATE_DIS			REG_BIT(4)
> +
>  #define XEHP_SLICE_UNIT_LEVEL_CLKGATE		XE_REG_MCR(0x94d4)
>  #define   L3_CR2X_CLKGATE_DIS			REG_BIT(17)
>  #define   L3_CLKGATE_DIS			REG_BIT(16)
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index 28b7f95b6c2f..d946b27ec4cd 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -251,6 +251,34 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
>  	},
>  
> +	/* Xe3_LPG */
> +
> +	{ XE_RTP_NAME("14021871409"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)),
> +	  XE_RTP_ACTIONS(SET(UNSLCGCTL9454, LSCFE_CLKGATE_DIS))
> +	},
> +
> +	/* Xe3_LPM */
> +
> +	{ XE_RTP_NAME("16021867713"),
> +	  XE_RTP_RULES(MEDIA_VERSION(3000),
> +		       ENGINE_CLASS(VIDEO_DECODE)),
> +	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F1C(0), MFXPIPE_CLKGATE_DIS)),
> +	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
> +	},
> +	{ XE_RTP_NAME("16021865536"),
> +	  XE_RTP_RULES(MEDIA_VERSION(3000),
> +		       ENGINE_CLASS(VIDEO_DECODE)),
> +	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
> +	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
> +	},
> +	{ XE_RTP_NAME("14021486841"),
> +	  XE_RTP_RULES(MEDIA_VERSION(3000), MEDIA_STEP(A0, B0),
> +		       ENGINE_CLASS(VIDEO_DECODE)),
> +	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), RAMDFTUNIT_CLKGATE_DIS)),
> +	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
> +	},
> +
>  	{}
>  };
>  
> @@ -567,6 +595,13 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>  			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
>  	},
>  
> +	/* Xe3_LPG */
> +
> +	{ XE_RTP_NAME("14021402888"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), FUNC(xe_rtp_match_first_render_or_compute)),
> +	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
> +	},
> +
>  	{}
>  };
>  
> @@ -734,6 +769,17 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
>  			     DIS_AUTOSTRIP))
>  	},
>  
> +	/* Xe3_LPG */
> +	{ XE_RTP_NAME("14021490052"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3000, 3001), ENGINE_CLASS(RENDER)),

This doesn't match what I see in the workaround database.  I only see
30.00 a-step as needing this workaround.

> +	  XE_RTP_ACTIONS(SET(FF_MODE,
> +			     DIS_MESH_PARTIAL_AUTOSTRIP |
> +			     DIS_MESH_AUTOSTRIP),
> +			 SET(VFLSKPD,
> +			     DIS_PARTIAL_AUTOSTRIP |
> +			     DIS_AUTOSTRIP))
> +	},
> +
>  	{}
>  };
>  
> diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
> index 920ca5060146..1949f8f3d7c2 100644
> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> @@ -33,6 +33,7 @@
>  		GRAPHICS_VERSION(2004)
>  22019338487	MEDIA_VERSION(2000)
>  		GRAPHICS_VERSION(2001)
> +		MEDIA_VERSION(3000)

This one is also A-step only as far as I can see.


Matt

>  22019338487_display	PLATFORM(LUNARLAKE)
>  16023588340	GRAPHICS_VERSION(2001)
>  14019789679	GRAPHICS_VERSION(1255)
> -- 
> 2.44.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

  reply	other threads:[~2024-09-11 18:03 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-06 21:51 [PATCH 0/9] Add Xe3 and Panther Lake support Matt Atwood
2024-09-06 21:51 ` [PATCH 1/9] drm/xe/xe3: Xe3 uses the same PAT settings as Xe2 Matt Atwood
2024-09-06 22:39   ` Rodrigo Vivi
2024-09-06 23:12     ` Lucas De Marchi
2024-09-06 21:51 ` [PATCH 2/9] drm/xe/xe3: Define Xe3 feature flags Matt Atwood
2024-09-06 23:34   ` Matt Roper
2024-09-06 21:51 ` [PATCH 3/9] drm/xe/xe3: Generate and store the L3 bank mask Matt Atwood
2024-09-06 23:43   ` Matt Roper
2024-09-09 12:15     ` Francois Dugast
2024-09-06 21:51 ` [PATCH 4/9] drm/xe/xe3: Add initial set of workarounds Matt Atwood
2024-09-11 18:03   ` Matt Roper [this message]
2024-09-06 21:51 ` [PATCH 5/9] drm/xe/xe3: Extend wa_15015404425 for xe3 Matt Atwood
2024-09-06 23:52   ` Matt Roper
2024-09-11 20:17     ` Matt Roper
2024-09-06 21:51 ` [PATCH 6/9] drm/xe/xe3lpm: Add new "instance0" steering table Matt Atwood
2024-09-06 21:51 ` [PATCH 7/9] drm/xe/ptl: PTL re-uses Xe2 MOCS table Matt Atwood
2024-09-10  6:16   ` Chauhan, Shekhar
2024-09-06 21:51 ` [PATCH 8/9] drm/xe/ptl: Add performance tuning settings for PTL Matt Atwood
2024-09-06 23:55   ` Matt Roper
2024-09-10  6:37     ` Chauhan, Shekhar
2024-09-06 21:51 ` [PATCH 9/9] drm/xe/ptl: Add PTL platform definition Matt Atwood
2024-09-06 23:56   ` Matt Roper
2024-09-12 16:56     ` Matt Roper
2024-09-06 23:31 ` ✗ CI.checkpatch: warning for Add Xe3 and Panther Lake support Patchwork
2024-09-06 23:32 ` ✓ CI.KUnit: success " Patchwork
2024-09-06 23:44 ` ✓ CI.Build: " Patchwork
2024-09-06 23:46 ` ✓ CI.Hooks: " Patchwork
2024-09-06 23:48 ` ✓ CI.checksparse: " Patchwork
2024-09-07  0:30 ` ✓ CI.BAT: " Patchwork

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