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Fri, 11 Oct 2024 21:49:27 +0000 Date: Fri, 11 Oct 2024 14:49:24 -0700 From: Matt Roper To: Matt Atwood CC: , , "Luca Coelho" Subject: Re: [PATCH v2 03/10] drm/i915/xe3lpd: Add new display power wells Message-ID: <20241011214924.GU4891@mdroper-desk1.amr.corp.intel.com> References: <20241010224311.50133-1-matthew.s.atwood@intel.com> <20241010224311.50133-4-matthew.s.atwood@intel.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20241010224311.50133-4-matthew.s.atwood@intel.com> X-ClientProxiedBy: BYAPR05CA0061.namprd05.prod.outlook.com (2603:10b6:a03:74::38) To DS0PR11MB8182.namprd11.prod.outlook.com (2603:10b6:8:163::17) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR11MB8182:EE_|DS7PR11MB7739:EE_ X-MS-Office365-Filtering-Correlation-Id: 25bd1062-5fee-411b-9c2c-08dcea3e93e8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?8rmDXd4sLItWzqsIeHsgZTGPguXjxDaNTxgF3w/mdtW/xFEa0f2WUOGeFDAy?= =?us-ascii?Q?bojsaiEBbimQIwhMQuY0wThjPKQZjSLg7P9s1lxoWSuemsCbF31OSR5y+efI?= =?us-ascii?Q?jofeFjCVA55mNUuq5XO3BlU3CpvKYPa0ozEsNW3ScCLbRJjF1kMcaKMqEZtf?= =?us-ascii?Q?9ebHYhYYx8ldpJxvZ5dzt1cm0E2CzLfb7ihvrAzWrR2nrHzgC0c+5EUGXzpv?= =?us-ascii?Q?eaqwgguucSSbuSMY+48n9A94MqTCGwso762tC5tlgHlvYgXf7BExrpsNyvXy?= =?us-ascii?Q?BCUaNtOUXLpPlSKIBedx4FJfBmONfdpKGF/+VSlhQaJVWL3ZrxDvV9E3sizd?= =?us-ascii?Q?I0edatXLxLPJ0mcvXhAVYv8juA1xo3k8+0tU6xPiLJK2vW40odJzAAfK74Fq?= =?us-ascii?Q?EpyIn3TdumUvCw/nR7Na7faJKITac6jRd1rwonw70M5IrFQYEQgcbw8vnhUK?= =?us-ascii?Q?A4aT3KuJ2sVIfkvmNEEVfdRKBRYZA/MuvcsEd64eyf+2R1BOIzApVk0P9rYs?= =?us-ascii?Q?XNHz5r9aHGP8SWAxj/6Gnn5kCrOsuqR1E3ST2aBteKKLl1+3Xiofagv1HCzG?= =?us-ascii?Q?oq0t7ycjHPYhneGx/XfLzoeMUz4piKwK0gJn2GVP9/vmAphBb9nwxKONkaYm?= =?us-ascii?Q?7uiYxLcfsZ2cHDFLGu5E9t6E8fCxsdTA/AvQaXhQ90+tDCcYZKxY4xOHo+bA?= =?us-ascii?Q?DKJ7Owdp9pAVhLKtzPZCOBjWf6fithRxqQKehA1cJ063We0pEFBhUC/x4KFs?= =?us-ascii?Q?sr1xkG+fxNJq6VAtvPJW45nDLpNRL+Y05zGLKOVEZZWctEoIgH4yN9lMwz1R?= =?us-ascii?Q?18zLDSQhsJ3isjOhD5aqUf3bUCy1IEjn5hVeHQCxDVRTtdVATLxsNx61r3D4?= =?us-ascii?Q?LqvsVGPUsa28DFogVkPNNgXXoCY7vQbHdWPNVoii+HAjp+uvPHODaKrjKThT?= =?us-ascii?Q?lL4YxG8n+xsn/6hPwNoBlVrjx345Kt8Xo04qtKFUAOuwHkpSS4W0ZJgJcmcy?= =?us-ascii?Q?xvKZEWvPfvL48WYnUFXpeSlxo9ulTIYLhtkpUoeyPI15Bxqqz0+H81MJyac9?= =?us-ascii?Q?/JuIe/b02kXyjjL4PgLwkLWIsZIcjnJoSe8B912G6xRqFDSB4ytndYDd0aVK?= =?us-ascii?Q?fkAyR3w/Yg95zG/Ncs3rfLAvw74LE5tybHjy7aVb/qjqMrmEQzXWbqlOfPcO?= =?us-ascii?Q?9VYYkL7NckdD4e3VdcqNgUG6Ym2Jh/RCXqeHoIYswDdeUM0Sl49iRohh5IQP?= =?us-ascii?Q?n7C0ZuLOyaax1eDLHhT+Vd+cS7Ti3TD3qrXwFU3mqw=3D=3D?= X-Forefront-Antispam-Report: CIP:255.255.255.255; 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Thanks for the patches and reviews. Matt > --- > .../i915/display/intel_display_power_map.c | 135 +++++++++++++++++- > 1 file changed, 134 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c > index 10948b3964ee..255b2c09607c 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c > @@ -1586,6 +1586,137 @@ static const struct i915_power_well_desc_list xe2lpd_power_wells[] = { > I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica), > }; > > +/* > + * Xe3 changes the power well hierarchy slightly from Xe_LPD+; PGB now > + * depends on PG1 instead of PG2: > + * > + * PG0 > + * | > + * --PG1-- > + * / | \ > + * PGA PGB PG2 > + * / \ > + * PGC PGD > + */ > + > +#define XE3LPD_PW_C_POWER_DOMAINS \ > + POWER_DOMAIN_PIPE_C, \ > + POWER_DOMAIN_PIPE_PANEL_FITTER_C > + > +#define XE3LPD_PW_D_POWER_DOMAINS \ > + POWER_DOMAIN_PIPE_D, \ > + POWER_DOMAIN_PIPE_PANEL_FITTER_D > + > +#define XE3LPD_PW_2_POWER_DOMAINS \ > + XE3LPD_PW_C_POWER_DOMAINS, \ > + XE3LPD_PW_D_POWER_DOMAINS, \ > + POWER_DOMAIN_TRANSCODER_C, \ > + POWER_DOMAIN_TRANSCODER_D, \ > + POWER_DOMAIN_VGA, \ > + POWER_DOMAIN_PORT_DDI_LANES_TC1, \ > + POWER_DOMAIN_PORT_DDI_LANES_TC2, \ > + POWER_DOMAIN_PORT_DDI_LANES_TC3, \ > + POWER_DOMAIN_PORT_DDI_LANES_TC4 > + > +I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_pw_2, > + XE3LPD_PW_2_POWER_DOMAINS, > + POWER_DOMAIN_INIT); > + > +I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_pw_b, > + POWER_DOMAIN_PIPE_B, > + POWER_DOMAIN_PIPE_PANEL_FITTER_B, > + POWER_DOMAIN_INIT); > + > +I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_pw_c, > + XE3LPD_PW_C_POWER_DOMAINS, > + POWER_DOMAIN_INIT); > + > +I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_pw_d, > + XE3LPD_PW_D_POWER_DOMAINS, > + POWER_DOMAIN_INIT); > + > +static const struct i915_power_well_desc xe3lpd_power_wells_main[] = { > + { > + .instances = &I915_PW_INSTANCES( > + I915_PW("PW_2", &xe3lpd_pwdoms_pw_2, > + .hsw.idx = ICL_PW_CTL_IDX_PW_2, > + .id = SKL_DISP_PW_2), > + ), > + .ops = &hsw_power_well_ops, > + .has_vga = true, > + .has_fuses = true, > + }, { > + .instances = &I915_PW_INSTANCES( > + I915_PW("PW_A", &xelpd_pwdoms_pw_a, > + .hsw.idx = XELPD_PW_CTL_IDX_PW_A), > + ), > + .ops = &hsw_power_well_ops, > + .irq_pipe_mask = BIT(PIPE_A), > + .has_fuses = true, > + }, { > + .instances = &I915_PW_INSTANCES( > + I915_PW("PW_B", &xe3lpd_pwdoms_pw_b, > + .hsw.idx = XELPD_PW_CTL_IDX_PW_B), > + ), > + .ops = &hsw_power_well_ops, > + .irq_pipe_mask = BIT(PIPE_B), > + .has_fuses = true, > + }, { > + .instances = &I915_PW_INSTANCES( > + I915_PW("PW_C", &xe3lpd_pwdoms_pw_c, > + .hsw.idx = XELPD_PW_CTL_IDX_PW_C), > + ), > + .ops = &hsw_power_well_ops, > + .irq_pipe_mask = BIT(PIPE_C), > + .has_fuses = true, > + }, { > + .instances = &I915_PW_INSTANCES( > + I915_PW("PW_D", &xe3lpd_pwdoms_pw_d, > + .hsw.idx = XELPD_PW_CTL_IDX_PW_D), > + ), > + .ops = &hsw_power_well_ops, > + .irq_pipe_mask = BIT(PIPE_D), > + .has_fuses = true, > + }, { > + .instances = &I915_PW_INSTANCES( > + I915_PW("AUX_A", &icl_pwdoms_aux_a, .xelpdp.aux_ch = AUX_CH_A), > + I915_PW("AUX_B", &icl_pwdoms_aux_b, .xelpdp.aux_ch = AUX_CH_B), > + I915_PW("AUX_TC1", &xelpdp_pwdoms_aux_tc1, .xelpdp.aux_ch = AUX_CH_USBC1), > + I915_PW("AUX_TC2", &xelpdp_pwdoms_aux_tc2, .xelpdp.aux_ch = AUX_CH_USBC2), > + I915_PW("AUX_TC3", &xelpdp_pwdoms_aux_tc3, .xelpdp.aux_ch = AUX_CH_USBC3), > + I915_PW("AUX_TC4", &xelpdp_pwdoms_aux_tc4, .xelpdp.aux_ch = AUX_CH_USBC4), > + ), > + .ops = &xelpdp_aux_power_well_ops, > + }, > +}; > + > +I915_DECL_PW_DOMAINS(xe3lpd_pwdoms_dc_off, > + POWER_DOMAIN_DC_OFF, > + XE3LPD_PW_2_POWER_DOMAINS, > + XE3LPD_PW_C_POWER_DOMAINS, > + XE3LPD_PW_D_POWER_DOMAINS, > + POWER_DOMAIN_AUDIO_MMIO, > + POWER_DOMAIN_INIT); > + > +static const struct i915_power_well_desc xe3lpd_power_wells_dcoff[] = { > + { > + .instances = &I915_PW_INSTANCES( > + I915_PW("DC_off", &xe3lpd_pwdoms_dc_off, > + .id = SKL_DISP_DC_OFF), > + ), > + .ops = &gen9_dc_off_power_well_ops, > + }, > +}; > + > + > +static const struct i915_power_well_desc_list xe3lpd_power_wells[] = { > + I915_PW_DESCRIPTORS(i9xx_power_wells_always_on), > + I915_PW_DESCRIPTORS(icl_power_wells_pw_1), > + I915_PW_DESCRIPTORS(xe3lpd_power_wells_dcoff), > + I915_PW_DESCRIPTORS(xe3lpd_power_wells_main), > + I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica), > +}; > + > static void init_power_well_domains(const struct i915_power_well_instance *inst, > struct i915_power_well *power_well) > { > @@ -1693,7 +1824,9 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains) > return 0; > } > > - if (DISPLAY_VER(i915) >= 20) > + if (DISPLAY_VER(i915) >= 30) > + return set_power_wells(power_domains, xe3lpd_power_wells); > + else if (DISPLAY_VER(i915) >= 20) > return set_power_wells(power_domains, xe2lpd_power_wells); > else if (DISPLAY_VER(i915) >= 14) > return set_power_wells(power_domains, xelpdp_power_wells); > -- > 2.45.0 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation