[PATCH 0/9] Add support for 3 VDSC engines 12 slices

[Ankit Nautiyal <ankit.k.nautiyal@intel.com>]

For BMG 3 VDSC engines are supported and each pipe can then support
3 slices. For Ultra joiner cases for modes like 8k@120 Hz we require
ultrajoiner and 3 x 4= 12 slices.
Add support for 3 VDSC engines and 12 DSC slices. Along with this
Pixel replication and Odd pixel considerartions are also required.

Rev2: Rebase

Ankit Nautiyal (9):
  drm/i915/display: Prepare for dsc 3 stream splitter
  drm/i915/vdsc: Use VDSC0/VDSC1 for LEFT/RIGHT VDSC engine
  drm/i915/vdsc: Add register bits for VDSC2 engine
  drm/i915/vdsc: Add support for read/write PPS for DSC3
  drm/i915/dp: Add check for hdisplay divisible by slice count
  drm/i915/display: Add DSC pixel replication
  drm/i915/dp: Compute pixel replication count for DSC 12 slices case
  drm/i915/dsc: Account for Odd pixel removal
  drm/i915/dp: Add support for 3 vdsc engines and 12 slices.

 drivers/gpu/drm/i915/display/icl_dsi.c        |   2 +-
 drivers/gpu/drm/i915/display/intel_display.c  |   3 +-
 .../drm/i915/display/intel_display_types.h    |   9 +-
 drivers/gpu/drm/i915/display/intel_dp.c       |  75 ++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp.h       |   2 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |   2 +
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 105 ++++++++++++++++--
 .../gpu/drm/i915/display/intel_vdsc_regs.h    |  22 +++-
 8 files changed, 200 insertions(+), 20 deletions(-)

-- 
2.45.2