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From: Matt Roper <matthew.d.roper@intel.com>
To: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: <intel-xe@lists.freedesktop.org>
Subject: Re: [PATCH] drm/xe/ptl: Apply Wa_14022866841
Date: Tue, 15 Oct 2024 17:00:30 -0700	[thread overview]
Message-ID: <20241016000030.GF5725@mdroper-desk1.amr.corp.intel.com> (raw)
In-Reply-To: <20241015234428.2004825-1-vinay.belgaumkar@intel.com>

On Tue, Oct 15, 2024 at 04:44:28PM -0700, Vinay Belgaumkar wrote:
> As part of this WA, GuC will hold a forcewake for certain
> MMIO accesses outside the GT/media domains.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>

Since we're not using doorbell submissions, activating the GuC
workaround should be all we need to do.  The KLV matches what's given in
the GuC spec, so

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>


> ---
>  drivers/gpu/drm/xe/abi/guc_klvs_abi.h | 1 +
>  drivers/gpu/drm/xe/xe_guc_ads.c       | 5 +++++
>  drivers/gpu/drm/xe/xe_wa_oob.rules    | 2 ++
>  3 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/abi/guc_klvs_abi.h b/drivers/gpu/drm/xe/abi/guc_klvs_abi.h
> index 6b30743a2f6c..37606cf8cc5e 100644
> --- a/drivers/gpu/drm/xe/abi/guc_klvs_abi.h
> +++ b/drivers/gpu/drm/xe/abi/guc_klvs_abi.h
> @@ -352,6 +352,7 @@ enum xe_guc_klv_ids {
>  	GUC_WORKAROUND_KLV_ID_DISABLE_MTP_DURING_ASYNC_COMPUTE				= 0x9007,
>  	GUC_WA_KLV_NP_RD_WRITE_TO_CLEAR_RCSM_AT_CGP_LATE_RESTORE			= 0x9008,
>  	GUC_WORKAROUND_KLV_ID_BACK_TO_BACK_RCS_ENGINE_RESET				= 0x9009,
> +	GUC_WA_KLV_WAKE_POWER_DOMAINS_FOR_OUTBOUND_MMIO					= 0x900a,
>  };
>  
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index 25292997c7f3..4e746ae98888 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -359,6 +359,11 @@ static void guc_waklv_init(struct xe_guc_ads *ads)
>  					GUC_WORKAROUND_KLV_ID_DISABLE_MTP_DURING_ASYNC_COMPUTE,
>  					&offset, &remain);
>  
> +	if (XE_WA(gt, 14022866841))
> +		guc_waklv_enable_simple(ads,
> +					GUC_WA_KLV_WAKE_POWER_DOMAINS_FOR_OUTBOUND_MMIO,
> +					&offset, &remain);
> +
>  	/*
>  	 * On RC6 exit, GuC will write register 0xB04 with the default value provided. As of now,
>  	 * the default value for this register is determined to be 0xC40. This could change in the
> diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
> index 264d6e116499..bcd04464b85e 100644
> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> @@ -39,3 +39,5 @@
>  14019789679	GRAPHICS_VERSION(1255)
>  		GRAPHICS_VERSION_RANGE(1270, 2004)
>  no_media_l3	MEDIA_VERSION(3000)
> +14022866841	GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)
> +		MEDIA_VERSION(3000), MEDIA_STEP(A0, B0)
> -- 
> 2.38.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

  reply	other threads:[~2024-10-16  0:00 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-10-15 23:44 [PATCH] drm/xe/ptl: Apply Wa_14022866841 Vinay Belgaumkar
2024-10-16  0:00 ` Matt Roper [this message]
2024-10-16  0:03 ` ✓ CI.Patch_applied: success for " Patchwork
2024-10-16  0:03 ` ✓ CI.checkpatch: " Patchwork
2024-10-16  0:05 ` ✓ CI.KUnit: " Patchwork
2024-10-16  0:16 ` ✓ CI.Build: " Patchwork
2024-10-16  0:18 ` ✓ CI.Hooks: " Patchwork
2024-10-16  0:20 ` ✓ CI.checksparse: " Patchwork
2024-10-16  0:38 ` ✓ CI.BAT: " Patchwork
2024-10-16 12:12 ` ✗ CI.FULL: failure " Patchwork
2024-10-16 23:24   ` Belgaumkar, Vinay

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