From: Matt Atwood <matthew.s.atwood@intel.com>
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: Suraj Kandpal <suraj.kandpal@intel.com>,
Matt Atwood <matthew.s.atwood@intel.com>
Subject: [PATCH v4 5/7] drm/i915/xe3lpd: Add new bit range of MAX swing setup
Date: Fri, 18 Oct 2024 13:03:09 -0700 [thread overview]
Message-ID: <20241018200311.67324-6-matthew.s.atwood@intel.com> (raw)
In-Reply-To: <20241018200311.67324-1-matthew.s.atwood@intel.com>
From: Suraj Kandpal <suraj.kandpal@intel.com>
Add new bit range for Max PHY Swing Setup in PORT_ALPM_CTL
register for DISPLAY_VER >= 30.
v2: implement as two seperate macros instead of a single macro
v3: extend previous definition by 2 bits that were previously reserved
Bspec: 70277
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 0841242543ca..9ad7611506e8 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -298,7 +298,7 @@
#define _PORT_ALPM_CTL_B 0x16fc2c
#define PORT_ALPM_CTL(port) _MMIO_PORT(port, _PORT_ALPM_CTL_A, _PORT_ALPM_CTL_B)
#define PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(31)
-#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK REG_GENMASK(23, 20)
+#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK REG_GENMASK(25, 20)
#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val)
#define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK REG_GENMASK(19, 16)
#define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK, val)
--
2.45.0
next prev parent reply other threads:[~2024-10-18 20:03 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-18 20:03 [PATCH v4 0/7] Add xe3lpd edp enabling Matt Atwood
2024-10-18 20:03 ` [PATCH v4 1/7] drm/i915/xe3lpd: Update pmdemand programming Matt Atwood
2024-10-21 12:41 ` Gustavo Sousa
2024-10-18 20:03 ` [PATCH v4 2/7] drm/i915/xe3lpd: Add cdclk changes Matt Atwood
2024-10-21 12:49 ` Gustavo Sousa
2024-10-18 20:03 ` [PATCH v4 3/7] drm/i915/xe3lpd: Disable HDCP Line Rekeying for Xe3 Matt Atwood
2024-10-23 17:52 ` Matt Roper
2024-10-24 2:52 ` Kandpal, Suraj
2024-10-25 18:58 ` Matt Roper
2024-10-28 4:11 ` Kandpal, Suraj
2024-10-30 0:02 ` Matt Roper
2024-11-04 3:44 ` Kandpal, Suraj
2024-10-18 20:03 ` [PATCH v4 4/7] drm/i915/xe3lpd: Add C20 Phy consolidated programming table Matt Atwood
2024-10-18 20:03 ` Matt Atwood [this message]
2024-10-18 23:38 ` [PATCH v4 5/7] drm/i915/xe3lpd: Add new bit range of MAX swing setup Matt Roper
2024-10-18 20:03 ` [PATCH v4 6/7] drm/i915/xe3lpd: Add check to see if edp over type c is allowed Matt Atwood
2024-10-21 12:22 ` Jani Nikula
2024-10-18 20:03 ` [PATCH v4 7/7] drm/i915/xe3lpd: Add condition for EDP to powerdown P2.PG Matt Atwood
2024-10-18 20:08 ` ✓ CI.Patch_applied: success for Add xe3lpd edp enabling (rev4) Patchwork
2024-10-18 20:08 ` ✗ CI.checkpatch: warning " Patchwork
2024-10-18 20:10 ` ✓ CI.KUnit: success " Patchwork
2024-10-18 20:28 ` ✓ CI.Build: " Patchwork
2024-10-18 20:31 ` ✓ CI.Hooks: " Patchwork
2024-10-18 20:32 ` ✗ CI.checksparse: warning " Patchwork
2024-10-18 21:20 ` ✗ CI.BAT: failure " Patchwork
2024-10-19 13:49 ` ✗ CI.FULL: " Patchwork
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