From: Clint Taylor <clinton.a.taylor@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Subject: [PATCH v4 04/11] drm/i915/ptl: Define IS_PANTHERLAKE macro
Date: Thu, 24 Oct 2024 15:31:07 -0700 [thread overview]
Message-ID: <20241024223114.785209-5-clinton.a.taylor@intel.com> (raw)
In-Reply-To: <20241024223114.785209-1-clinton.a.taylor@intel.com>
From: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Common display code requires IS_PANTHERLAKE macro.
Define the macro and set 0 as PTL is no longer support for i915.
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a66e5bb078cf..ca1ab5931e28 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -538,6 +538,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
*/
#define IS_LUNARLAKE(i915) (0 && i915)
#define IS_BATTLEMAGE(i915) (0 && i915)
+#define IS_PANTHERLAKE(i915) (0 && i915)
#define IS_ARROWLAKE(i915) \
IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL)
--
2.25.1
next prev parent reply other threads:[~2024-10-24 22:31 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-24 22:31 [PATCH v4 00/11] drm/i915/xe3lpd: ptl display patches Clint Taylor
2024-10-24 22:31 ` [PATCH v4 01/11] drm/i915/xe3lpd: Update pmdemand programming Clint Taylor
2024-10-25 13:31 ` Gustavo Sousa
2024-10-25 14:16 ` Jani Nikula
2024-10-24 22:31 ` [PATCH v4 02/11] drm/i915/xe3lpd: Disable HDCP Line Rekeying for Xe3 Clint Taylor
2024-10-24 22:31 ` [PATCH v4 03/11] drm/i915/xe3lpd: Add check to see if edp over type c is allowed Clint Taylor
2024-10-25 5:00 ` Murthy, Arun R
2024-10-25 15:29 ` Jani Nikula
2024-10-24 22:31 ` Clint Taylor [this message]
2024-10-24 22:31 ` [PATCH v4 05/11] drm/i915/cx0: Extend C10 check to PTL Clint Taylor
2024-10-24 22:31 ` [PATCH v4 06/11] drm/i915/cx0: Remove bus reset after every c10 transaction Clint Taylor
2024-10-25 13:52 ` Gustavo Sousa
2024-10-24 22:31 ` [PATCH v4 07/11] drm/i915/xe3lpd: Move async flip bit to PLANE_SURF register Clint Taylor
2024-10-24 22:31 ` [PATCH v4 08/11] drm/i915/xe3: Underrun recovery does not exist post Xe2 Clint Taylor
2024-10-24 22:31 ` [PATCH v4 09/11] drm/i915/display/xe3: disable x-tiled framebuffers Clint Taylor
2024-10-24 22:31 ` [PATCH v4 10/11] drm/i915/xe3lpd: Skip disabling VRR during modeset disable Clint Taylor
2024-10-25 8:06 ` Golani, Mitulkumar Ajitkumar
2024-10-25 10:18 ` Golani, Mitulkumar Ajitkumar
2024-10-24 22:31 ` [PATCH v4 11/11] drm/i915/xe3lpd: Power request asserting/deasserting Clint Taylor
2024-10-25 13:58 ` Gustavo Sousa
2024-10-25 4:27 ` ✓ CI.Patch_applied: success for drm/i915/xe3lpd: ptl display patches (rev4) Patchwork
2024-10-25 4:27 ` ✗ CI.checkpatch: warning " Patchwork
2024-10-25 4:28 ` ✓ CI.KUnit: success " Patchwork
2024-10-25 4:40 ` ✓ CI.Build: " Patchwork
2024-10-25 4:42 ` ✓ CI.Hooks: " Patchwork
2024-10-25 4:43 ` ✗ CI.checksparse: warning " Patchwork
2024-10-25 5:08 ` ✗ CI.BAT: failure " Patchwork
2024-10-26 14:44 ` ✗ CI.FULL: " Patchwork
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