Re: [PATCH v2] drm/xe: Mark ComputeCS read mode as UC on iGPU

[Matt Roper <matthew.d.roper@intel.com>]

On Mon, Jan 13, 2025 at 04:25:07PM -0800, Matthew Brost wrote:
> RING_CMD_CCTL read index should be UC on iGPU parts due to L3 caching
> structure. Having this as WB blocks ULLS from being enabled. Change to
> UC to unblock ULLS on iGPU.
> 
> v2:
>  - Drop internal communications commnet, bspec is updated
> 
> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
> Cc: Michal Mrozek <michal.mrozek@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: stable@vger.kernel.org
> Fixes: 328e089bfb37 ("drm/xe: Leverage ComputeCS read L3 caching")
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> Acked-by: Michal Mrozek <michal.mrozek@intel.com>
> Reviewed-by: Stuart Summers <stuart.summers@intel.com>

Matches the bspec update that landed last month.

Bspec: 72161
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>


Matt

> ---
>  drivers/gpu/drm/xe/xe_hw_engine.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index ac9c666a9652..fc447751fe78 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -422,7 +422,7 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe)
>  	 * Bspec: 72161
>  	 */
>  	const u8 mocs_write_idx = gt->mocs.uc_index;
> -	const u8 mocs_read_idx = hwe->class == XE_ENGINE_CLASS_COMPUTE &&
> +	const u8 mocs_read_idx = hwe->class == XE_ENGINE_CLASS_COMPUTE && IS_DGFX(xe) &&
>  				 (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) ?
>  				 gt->mocs.wb_index : gt->mocs.uc_index;
>  	u32 ring_cmd_cctl_val = REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, mocs_write_idx) |
> -- 
> 2.34.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation