From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 43279C02181 for ; Thu, 23 Jan 2025 01:14:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E592510E3CA; Thu, 23 Jan 2025 01:14:26 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="jZiPFZkX"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4D03710E152 for ; Thu, 23 Jan 2025 01:14:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737594863; x=1769130863; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hVTFnmfvm3H8qcrh2Q9ZCZS5doqesc9ikOS7XetrTBc=; b=jZiPFZkXpiXMuQIacEWTJf/AI0DMm615WTWbqDS7dfV9PhKbGjFdMNxF HHJ09xR2wa/AVaOLT9KObQNpmTub6GUll3Y9L4VgoWFLoWyr9OavD1QZz 9cXgzb3ye01AGcp7I5piEl9lP8IioJJfzlU8hxYg4Mgbqjvqa3IirRnWe OyKX5PXJ2G22xw1yGMsa1EjTOFKebz8NVSKFWq1iaQWFoO93gBToqQsLx hMjrowlKkxzW2VsOolyddPI7obepCKi5UCeUnxoJduTUXmmBDs2j3Eyut v8ajjihMcV7a4eWXgviY3dzPNt5yRIVCPo87bElWmAl2/8nwIPlQZm2tK w==; X-CSE-ConnectionGUID: ztC6KvkiQESSvKnIgT+t9w== X-CSE-MsgGUID: auANc5HESX+ORN5B0OTZUQ== X-IronPort-AV: E=McAfee;i="6700,10204,11323"; a="37967065" X-IronPort-AV: E=Sophos;i="6.13,226,1732608000"; d="scan'208";a="37967065" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2025 17:14:22 -0800 X-CSE-ConnectionGUID: zkxGfu3PS/ahS/XXqTaurA== X-CSE-MsgGUID: rhf4OINAQ62gtxiElbvGnA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,226,1732608000"; d="scan'208";a="107124122" Received: from lstrano-desk.jf.intel.com ([10.54.39.91]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2025 17:14:22 -0800 From: Matthew Brost To: intel-xe@lists.freedesktop.org Cc: jose.souza@intel.com, lionel.g.landwerlin@intel.com, carlos.santa@intel.com, rodrigo.vivi@intel.com Subject: [RFC PATCH 5/6] drm/xe: Add replay_offset and replay_length lines to LRC HWCTX snapshot Date: Wed, 22 Jan 2025 17:15:12 -0800 Message-Id: <20250123011513.362430-6-matthew.brost@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250123011513.362430-1-matthew.brost@intel.com> References: <20250123011513.362430-1-matthew.brost@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Add replay_offset and replay_length lines to LRC HWCTX snapshot with the idea being this information can be used extract the data which needs to be pass to exec queue extension DRM_XE_EXEC_QUEUE_SET_HANG_REPLAY_STATE so GPU hang can be replayed via a Mesa tool. The additional lines look like: [HWCTX].replay_offset: 0x%x [HWCTX].replay_length: 0x%x Cc: José Roberto de Souza Signed-off-by: Matthew Brost --- drivers/gpu/drm/xe/xe_lrc.c | 8 ++++++++ drivers/gpu/drm/xe/xe_lrc.h | 1 + drivers/gpu/drm/xe/xe_lrc_types.h | 3 +++ 3 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c index bbb9ffbf6367..1ad3ab59fce2 100644 --- a/drivers/gpu/drm/xe/xe_lrc.c +++ b/drivers/gpu/drm/xe/xe_lrc.c @@ -896,6 +896,9 @@ static int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe, kref_init(&lrc->refcount); lrc->flags = 0; + lrc->replay_size = xe_gt_lrc_size(gt, hwe->class); + if (xe_gt_has_indirect_ring_state(gt)) + lrc->replay_size -= LRC_INDIRECT_RING_STATE_SIZE; lrc_size = ring_size + xe_gt_lrc_size(gt, hwe->class); if (xe_gt_has_indirect_ring_state(gt)) lrc->flags |= XE_LRC_FLAG_INDIRECT_RING_STATE; @@ -1671,6 +1674,8 @@ struct xe_lrc_snapshot *xe_lrc_snapshot_capture(struct xe_lrc *lrc) snapshot->lrc_bo = xe_bo_get(lrc->bo); snapshot->lrc_offset = xe_lrc_pphwsp_offset(lrc); snapshot->lrc_size = lrc->bo->size - snapshot->lrc_offset; + snapshot->replay_offset = 0; + snapshot->replay_size = lrc->replay_size; snapshot->lrc_snapshot = NULL; snapshot->ctx_timestamp = xe_lrc_ctx_timestamp(lrc); snapshot->ctx_job_timestamp = xe_lrc_ctx_job_timestamp(lrc); @@ -1745,6 +1750,9 @@ void xe_lrc_snapshot_print(struct xe_lrc_snapshot *snapshot, struct drm_printer } drm_printf(p, "\n\t[HWCTX].length: 0x%lx\n", snapshot->lrc_size - LRC_PPHWSP_SIZE); + drm_printf(p, "\n\t[HWCTX].replay_offset: 0x%lx\n", snapshot->replay_offset); + drm_printf(p, "\n\t[HWCTX].replay_length: 0x%lx\n", snapshot->replay_size); + drm_puts(p, "\t[HWCTX].data: "); for (; i < snapshot->lrc_size; i += sizeof(u32)) { u32 *val = snapshot->lrc_snapshot + i; diff --git a/drivers/gpu/drm/xe/xe_lrc.h b/drivers/gpu/drm/xe/xe_lrc.h index 4206e6a8b50a..848d64511ca8 100644 --- a/drivers/gpu/drm/xe/xe_lrc.h +++ b/drivers/gpu/drm/xe/xe_lrc.h @@ -23,6 +23,7 @@ struct xe_lrc_snapshot { struct xe_bo *lrc_bo; void *lrc_snapshot; unsigned long lrc_size, lrc_offset; + unsigned long replay_size, replay_offset; u32 context_desc; u32 ring_addr; diff --git a/drivers/gpu/drm/xe/xe_lrc_types.h b/drivers/gpu/drm/xe/xe_lrc_types.h index 71ecb453f811..c2766719ff77 100644 --- a/drivers/gpu/drm/xe/xe_lrc_types.h +++ b/drivers/gpu/drm/xe/xe_lrc_types.h @@ -25,6 +25,9 @@ struct xe_lrc { /** @size: size of lrc including any indirect ring state page */ u32 size; + /** @replay_size: Size LRC needed for replaying a hang */ + u32 replay_size; + /** @tile: tile which this LRC belongs to */ struct xe_tile *tile; -- 2.34.1