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From: Aradhya Bhatia <aradhya.bhatia@intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: Intel XE List <intel-xe@lists.freedesktop.org>,
	Lucas De Marchi <lucas.demarchi@intel.com>,
	Tejas Upadhyay <tejas.upadhyay@intel.com>,
	Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>,
	Aradhya Bhatia <aradhya.bhatia@intel.com>
Subject: [PATCH v4 1/2] drm/xe: Add Wa_16021333562 and Wa_14016712196
Date: Thu, 30 Jan 2025 05:59:38 +0000	[thread overview]
Message-ID: <20250130055939.282988-2-aradhya.bhatia@intel.com> (raw)
In-Reply-To: <20250130055939.282988-1-aradhya.bhatia@intel.com>

Wa_16021333562 and Wa_14016712196 are permanent workarounds that apply
to multiple platforms. Wa_16021333562 applies to platforms ranging from
TGL (12.00) to Xe_LPM (13.00), while Wa_14016712196 from DG2 (12.55) to
Xe_LPG (12.74).

Signed-off-by: Aradhya Bhatia <aradhya.bhatia@intel.com>
---
 drivers/gpu/drm/xe/xe_guc_ads.c    | 2 +-
 drivers/gpu/drm/xe/xe_ring_ops.c   | 4 ++++
 drivers/gpu/drm/xe/xe_wa_oob.rules | 4 ++++
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index fab259adc380..e7c9e095a19f 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -342,7 +342,7 @@ static void guc_waklv_init(struct xe_guc_ads *ads)
 	offset = guc_ads_waklv_offset(ads);
 	remain = guc_ads_waklv_size(ads);
 
-	if (XE_WA(gt, 14019882105))
+	if (XE_WA(gt, 14019882105) || XE_WA(gt, 16021333562))
 		guc_waklv_enable_simple(ads,
 					GUC_WORKAROUND_KLV_BLOCK_INTERRUPTS_WHEN_MGSR_BLOCKED,
 					&offset, &remain);
diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
index 9f327f27c072..29cd7b548493 100644
--- a/drivers/gpu/drm/xe/xe_ring_ops.c
+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
@@ -192,6 +192,10 @@ static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i)
 	else if (job->q->class == XE_ENGINE_CLASS_COMPUTE)
 		flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
 
+	if (XE_WA(gt, 14016712196))
+		i = emit_pipe_control(dw, i, 0, PIPE_CONTROL_DEPTH_CACHE_FLUSH,
+				      LRC_PPHWSP_SCRATCH_ADDR, 0);
+
 	return emit_pipe_control(dw, i, PIPE_CONTROL0_HDC_PIPELINE_FLUSH, flags, 0, 0);
 }
 
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index 228436532282..ea72bcc02e1e 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -43,3 +43,7 @@
 no_media_l3	MEDIA_VERSION(3000)
 14022866841	GRAPHICS_VERSION(3000), GRAPHICS_STEP(A0, B0)
 		MEDIA_VERSION(3000), MEDIA_STEP(A0, B0)
+16021333562	GRAPHICS_VERSION_RANGE(1200, 1274)
+		MEDIA_VERSION(1300)
+14016712196	GRAPHICS_VERSION(1255)
+		GRAPHICS_VERSION_RANGE(1270, 1274)
-- 
2.45.2


  reply	other threads:[~2025-01-30  5:59 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-30  5:59 [PATCH v4 0/2]drm/xe: Add and refactor workarounds Aradhya Bhatia
2025-01-30  5:59 ` Aradhya Bhatia [this message]
2025-01-30 12:04   ` [PATCH v4 1/2] drm/xe: Add Wa_16021333562 and Wa_14016712196 Upadhyay, Tejas
2025-02-18 16:20   ` Lucas De Marchi
2025-01-30  5:59 ` [PATCH v4 2/2] drm/xe/oa: Refactor WAs to use XE_WA() macro Aradhya Bhatia
2025-01-30 18:37   ` Lucas De Marchi
2025-01-30  6:13 ` ✓ CI.Patch_applied: success for drm/xe: Add and refactor workarounds (rev3) Patchwork
2025-01-30  6:13 ` ✓ CI.checkpatch: " Patchwork
2025-01-30  6:14 ` ✓ CI.KUnit: " Patchwork
2025-01-30  6:31 ` ✓ CI.Build: " Patchwork
2025-01-30  6:33 ` ✓ CI.Hooks: " Patchwork
2025-01-30  6:34 ` ✓ CI.checksparse: " Patchwork
2025-01-30  6:57 ` ✓ Xe.CI.BAT: " Patchwork
2025-01-31  7:36 ` ✗ Xe.CI.Full: failure " Patchwork
2025-02-18 13:01   ` Aradhya Bhatia

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