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From: Gustavo Sousa <gustavo.sousa@intel.com>
To: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: Luca Coelho <luciano.coelho@intel.com>
Subject: [PATCH] drm/i915/dmc_wl: Track INITIATE_PM_DMD_REQ for DC5
Date: Mon,  3 Feb 2025 17:58:58 -0300	[thread overview]
Message-ID: <20250203205941.251754-1-gustavo.sousa@intel.com> (raw)

The Bspec has been updated to include INITIATE_PM_DMD_REQ in the set of
register offsets that require the DMC wakelock for access during DC5.
Update our table accordingly.

Bspec: 71583
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc_wl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
index 43884740f8ea..86ba159b683c 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
@@ -102,6 +102,7 @@ static const struct intel_dmc_wl_range xe3lpd_dc5_dc6_dmc_ranges[] = {
 	{ .start = 0x42088 }, /* CHICKEN_MISC_3 */
 	{ .start = 0x46160 }, /* CMTG_CLK_SEL */
 	{ .start = 0x8f000, .end = 0x8ffff }, /* Main DMC registers */
+	{ .start = 0x45230 }, /* INITIATE_PM_DMD_REQ */
 
 	{},
 };
-- 
2.48.1


             reply	other threads:[~2025-02-03 20:59 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-03 20:58 Gustavo Sousa [this message]
2025-02-03 21:25 ` ✓ CI.Patch_applied: success for drm/i915/dmc_wl: Track INITIATE_PM_DMD_REQ for DC5 Patchwork
2025-02-03 21:26 ` ✓ CI.checkpatch: " Patchwork
2025-02-03 21:27 ` ✓ CI.KUnit: " Patchwork
2025-02-03 21:43 ` ✓ CI.Build: " Patchwork
2025-02-03 21:45 ` ✓ CI.Hooks: " Patchwork
2025-02-03 21:47 ` ✓ CI.checksparse: " Patchwork
2025-02-03 22:06 ` ✓ Xe.CI.BAT: " Patchwork
2025-02-04  0:22 ` ✗ Xe.CI.Full: failure " Patchwork
2025-02-04 11:38   ` Gustavo Sousa
2025-02-04  8:46 ` [PATCH] " Luca Coelho
2025-02-04 12:50   ` Gustavo Sousa

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