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From: Pekka Paalanen <pekka.paalanen@haloniitty.fi>
To: "Murthy, Arun R" <arun.r.murthy@intel.com>
Cc: <intel-xe@lists.freedesktop.org>,
	<intel-gfx@lists.freedesktop.org>,
	<dri-devel@lists.freedesktop.org>, <suraj.kandpal@intel.com>,
	<dmitry.baryshkov@linaro.org>
Subject: Re: [PATCH v8 01/14] drm: Define histogram structures exposed to user
Date: Thu, 20 Feb 2025 17:50:47 +0200	[thread overview]
Message-ID: <20250220175047.412ee8d4@eldfell> (raw)
In-Reply-To: <cd095fd7-3043-402a-9e21-c0c85c53f8e3@intel.com>

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On Wed, 19 Feb 2025 09:28:51 +0530
"Murthy, Arun R" <arun.r.murthy@intel.com> wrote:

> On 18-02-2025 21:48, Pekka Paalanen wrote:
> > On Tue, 18 Feb 2025 11:13:39 +0530
> > "Murthy, Arun R"<arun.r.murthy@intel.com> wrote:
> >  
> >> On 17-02-2025 15:38, Pekka Paalanen wrote:  
> >>> Hi Arun,
> >>>
> >>> this whole series seems to be missing all the UAPI docs for the DRM
> >>> ReST files, e.g. drm-kms.rst. The UAPI header doc comments are not a
> >>> replacement for them, I would assume both are a requirement.
> >>>
> >>> Without the ReST docs it is really difficult to see how this new UAPI
> >>> should be used.  
> >> Hi Pekka,
> >> I also realized later on this. Will add this in my next patchset.  
> >>> On Tue, 28 Jan 2025 21:21:07 +0530
> >>> Arun R Murthy<arun.r.murthy@intel.com> wrote:
> >>>     
> >>>> Display Histogram is an array of bins and can be generated in many ways
> >>>> referred to as modes.
> >>>> Ex: HSV max(RGB), Wighted RGB etc.
> >>>>
> >>>> Understanding the histogram data format(Ex: HSV max(RGB))
> >>>> Histogram is just the pixel count.
> >>>> For a maximum resolution of 10k (10240 x 4320 = 44236800)
> >>>> 25 bits should be sufficient to represent this along with a buffer of 7
> >>>> bits(future use) u32 is being considered.
> >>>> max(RGB) can be 255 i.e 0xFF 8 bit, considering the most significant 5
> >>>> bits, hence 32 bins.
> >>>> Below mentioned algorithm illustrates the histogram generation in
> >>>> hardware.
> >>>>
> >>>> hist[32] = {0};
> >>>> for (i = 0; i < resolution; i++) {
> >>>> 	bin = max(RGB[i]);
> >>>> 	bin = bin >> 3;	/* consider the most significant bits */
> >>>> 	hist[bin]++;
> >>>> }
> >>>> If the entire image is Red color then max(255,0,0) is 255 so the pixel
> >>>> count of each pixels will be placed in the last bin. Hence except
> >>>> hist[31] all other bins will have a value zero.
> >>>> Generated histogram in this case would be hist[32] = {0,0,....44236800}
> >>>>
> >>>> Description of the structures, properties defined are documented in the
> >>>> header file include/uapi/drm/drm_mode.h
> >>>>
> >>>> v8: Added doc for HDR planes, removed reserved variables (Dmitry)
> >>>>
> >>>> Signed-off-by: Arun R Murthy<arun.r.murthy@intel.com>
> >>>> ---
> >>>>    include/uapi/drm/drm_mode.h | 65 +++++++++++++++++++++++++++++++++++++++++++++
> >>>>    1 file changed, 65 insertions(+)
> >>>>
> >>>> diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
> >>>> index c082810c08a8b234ef2672ecf54fc8c05ddc2bd3..b8b7b18843ae7224263a9c61b20ac6cbf5df69e9 100644
> >>>> --- a/include/uapi/drm/drm_mode.h
> >>>> +++ b/include/uapi/drm/drm_mode.h
> >>>> @@ -1355,6 +1355,71 @@ struct drm_mode_closefb {
> >>>>    	__u32 pad;
> >>>>    };
> >>>>    
> >>>> +/**
> >>>> + * enum drm_mode_histogram
> >>>> + *
> >>>> + * @DRM_MODE_HISTOGRAM_HSV_MAX_RGB:
> >>>> + * Maximum resolution at present 10k, 10240x4320 = 44236800
> >>>> + * can be denoted in 25bits. With an additional 7 bits in buffer each bin
> >>>> + * can be a u32 value.
> >>>> + * For SDL, Maximum value of max(RGB) is 255, so max 255 bins.  
> >>> I assume s/SDL/SDR/.  
> >> Yes, sorry TYPO  
> >>> This assumption seems false. SDR can be also 10-bit and probably even
> >>> more.  
> >> Yes but in practice majority of them being 8-bit. So have considered
> >> 8-bit for illustration purpose only.
> >> The design itself should accommodate 10-bit as well.  
> > Hi Arun,
> >
> > if these are just examples, then there is no need to mention SDR or
> > HDR. You can say that if "thing" is 8-bit, then there are 256 possible
> > values, and we could have 256 bins or we could have just 32 bins.
> >
> > But what is "thing"? Let's see below.  
> Sure will remove these over here and add then in the ReST document.
> >>>> + * If the most significant 5 bits are considered, then bins = 2^5
> >>>> + * will be 32 bins.
> >>>> + * For HDR, maximum value of max(RGB) is 65535, so max 65535 bins.  
> >>> Does this mean that the histogram is computed on the pixel values
> >>> emitted to the cable? What if the cable format is YUV?  
> >> Yes, again the illustration over here is max(RGB) used for histogram
> >> generation.
> >> If YUV is used or weighted RGB is used for histogram generation then the
> >> mode will have to change and accordingly the data for that mode.  
> > Do you mean that the HDMI or DisplayPort signalling mode (YUV vs. RGB?
> > sub-sampling? bit-depth?) affects which histogram modes can be used?  
> No this is actually for user as to how to interpret the histogram data 
> that is being sent from the KMD. UMD reads this histogram so in order to 
> understand the format of this data he needs to know the histogram mode.
> > Currently userspace cannot know or control the signalling mode. How
> > would userspace know which histogram modes are possible?  
> As part of drm_histogram_caps struct under HISTOGRAM_CAPS property KMD 
> will expose all of the supported histogram modes to the user. User will 
> then choose one among the supported modes by drm_histogram_config 
> struct(HISTOGRAM_ENABLE property)
> > You should also define at which point of the pixel pipeline the
> > histogram is recorded. Is it before, say, CRTC DEGAMMA processing? Is
> > it after signal encoding to the 6/8/10/12/14/16-bit RGB or YUV format?
> > Before or after YUV sub-sampling? Limited or full range?  
> This again is the hardware design. Theoretically this histogram hardware 
> will be at the end of the hardware pipe, i.e after hardware/software 
> composition is done.

Hi Arun,

sure, it may be by hardware design, but the UAPI must specify or
communicate exactly what it is. This seems to be the recurring theme in
all the remaining comments, so I trimmed them away.

A generic UAPI is mandatory, because that's KMS policy AFAIU. A generic
UAPI cannot key anything off of the hardware revision. Instead,
everything must be specified and communicated explicitly. It's good if
AMD has similar functionality, someone from their team could take a
look so you can come up with an UAPI that works for both.

Dmitry Baryshkov tried to ask for the same thing. Assuming I know
nothing about the hardware, and the only documentation I have is the
KMS UAPI documentation (userland side, not kernel internals), I should
be able to write a program from scratch that correctly records and
analyses the histogram on every piece of hardware where the kernel
driver exposes it. That means explaining exactly what the driver and the
hardware will do when I poke that UAPI.


Thanks,
pq

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  reply	other threads:[~2025-02-20 15:51 UTC|newest]

Thread overview: 63+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-28 15:51 [PATCH v8 00/14] Display Global Histogram Arun R Murthy
2025-01-28 15:51 ` [PATCH v8 01/14] drm: Define histogram structures exposed to user Arun R Murthy
2025-02-14  6:38   ` Kandpal, Suraj
2025-02-14  8:38     ` Kandpal, Suraj
2025-03-13  6:10     ` Murthy, Arun R
2025-02-17 10:08   ` Pekka Paalanen
2025-02-17 12:27     ` Pekka Paalanen
2025-03-03  7:52       ` Murthy, Arun R
2025-03-03  9:33         ` Pekka Paalanen
2025-02-17 17:26     ` Simona Vetter
2025-02-17 22:23       ` Simona Vetter
2025-02-18  6:01       ` Murthy, Arun R
2025-02-19 13:31       ` Simona Vetter
2025-03-03  7:50         ` Murthy, Arun R
2025-02-18  5:43     ` Murthy, Arun R
2025-02-18 16:18       ` Pekka Paalanen
2025-02-19  3:58         ` Murthy, Arun R
2025-02-20 15:50           ` Pekka Paalanen [this message]
2025-03-03  7:53             ` Murthy, Arun R
2025-03-03  9:20               ` Pekka Paalanen
2025-03-19 12:08                 ` Murthy, Arun R
2025-03-20  9:23                   ` Pekka Paalanen
2025-03-26  6:03                     ` Murthy, Arun R
2025-03-27  8:59                       ` Pekka Paalanen
2025-03-28  5:06                         ` Murthy, Arun R
2025-04-17  6:31                           ` Shankar, Uma
2025-04-17  7:18                             ` Pekka Paalanen
2025-04-17 10:50                               ` Shankar, Uma
2025-02-20 16:26       ` Dmitry Baryshkov
2025-03-03  7:54         ` Murthy, Arun R
2025-01-28 15:51 ` [PATCH v8 02/14] drm: Define ImageEnhancemenT LUT " Arun R Murthy
2025-02-14  9:11   ` Kandpal, Suraj
2025-01-28 15:51 ` [PATCH v8 03/14] drm/crtc: Expose API to create drm crtc property for histogram Arun R Murthy
2025-02-14  9:36   ` Kandpal, Suraj
2025-01-28 15:51 ` [PATCH v8 04/14] drm/crtc: Expose API to create drm crtc property for IET LUT Arun R Murthy
2025-02-14  9:47   ` Kandpal, Suraj
2025-01-28 15:51 ` [PATCH v8 05/14] drm/i915/histogram: Define registers for histogram Arun R Murthy
2025-01-28 15:51 ` [PATCH v8 06/14] drm/i915/histogram: Add support " Arun R Murthy
2025-02-14 10:02   ` Kandpal, Suraj
2025-02-14 10:24     ` Kandpal, Suraj
2025-02-17  6:09       ` Kandpal, Suraj
2025-02-16 14:32   ` [v8,06/14] " Thasleem, Mohammed
2025-01-28 15:51 ` [PATCH v8 07/14] drm/xe: Add histogram support to Xe builds Arun R Murthy
2025-01-28 15:51 ` [PATCH v8 08/14] drm/i915/histogram: histogram interrupt handling Arun R Murthy
2025-02-14 10:19   ` Kandpal, Suraj
2025-01-28 15:51 ` [PATCH v8 09/14] drm/i915/histogram: Hook i915 histogram with drm histogram Arun R Murthy
2025-02-14 10:22   ` Kandpal, Suraj
2025-01-28 15:51 ` [PATCH v8 10/14] drm/i915/iet: Add support to writing the IET LUT data Arun R Murthy
2025-02-17  4:23   ` Kandpal, Suraj
2025-01-28 15:51 ` [PATCH v8 11/14] drm/i915/crtc: Hook i915 IET LUT with the drm IET properties Arun R Murthy
2025-01-28 15:51 ` [PATCH v8 12/14] drm/i915/histogram: histogram delay counter doesnt reset Arun R Murthy
2025-01-28 15:51 ` [PATCH v8 13/14] drm/i915/histogram: Histogram changes for Display 20+ Arun R Murthy
2025-02-17  6:25   ` Kandpal, Suraj
2025-01-28 15:51 ` [PATCH v8 14/14] drm/i915/histogram: Enable pipe dithering Arun R Murthy
2025-02-17  6:20   ` Kandpal, Suraj
2025-01-28 18:16 ` ✓ CI.Patch_applied: success for Display Global Histogram (rev9) Patchwork
2025-01-28 18:16 ` ✗ CI.checkpatch: warning " Patchwork
2025-01-28 18:18 ` ✓ CI.KUnit: success " Patchwork
2025-01-28 18:47 ` ✓ CI.Build: " Patchwork
2025-01-28 18:49 ` ✗ CI.Hooks: failure " Patchwork
2025-01-28 18:50 ` ✗ CI.checksparse: warning " Patchwork
2025-01-28 19:24 ` ✓ Xe.CI.BAT: success " Patchwork
2025-01-29  7:39 ` ✗ Xe.CI.Full: failure " Patchwork

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