From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E3CC0C282D0 for ; Fri, 28 Feb 2025 09:38:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A366710EC44; Fri, 28 Feb 2025 09:38:41 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Havy6Pyj"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8D08010EC47; Fri, 28 Feb 2025 09:38:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740735518; x=1772271518; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=e0QO+axlk64veADD4h4oba76vnaNHt8uEWfo+MNpd5E=; b=Havy6PyjfZGcs++iU0GA+HTAvzAmbGfXzHecZiTESxYHIxlZi421WjK2 gH9nEdMXAUttAveKB4VRKxJdWrdw3OlZJYmZv5oTGX//RoqhVTnjM0Hhw S47qb5vhmqUBJOu6JnT7FODxdU1gXdWaGdvJ3kZTi9eQiKxpFOE3H0w9k T7fhZVgJeQJWdANeJ/2eI4ngGcnSfI3vb+Hrx/oVdKnIuKB7eoRXE9FD2 ACiz0UOnfT4Y8qnj29eVrK5q4EEChsCONNhnbU1WJ/ouIeY2Jib1zKN4f Epv4rVV+uaH3D7fGStBnjImGfdMqy3i/kWAs5Bzabqcl385TXc755UO6e A==; X-CSE-ConnectionGUID: DTwfa5CgRTKYBUyGP/6Ecw== X-CSE-MsgGUID: qNHCsgeoSIeqGW+DSEG9eQ== X-IronPort-AV: E=McAfee;i="6700,10204,11358"; a="52293082" X-IronPort-AV: E=Sophos;i="6.13,322,1732608000"; d="scan'208";a="52293082" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2025 01:38:37 -0800 X-CSE-ConnectionGUID: jBom/Y/NReOdudrfqMzgrQ== X-CSE-MsgGUID: XE3RQHtKTXSGaiH2OznGhA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="154466510" Received: from klitkey1-mobl1.ger.corp.intel.com (HELO vgovind2-mobl3.intel.com) ([10.245.246.23]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2025 01:38:35 -0800 From: Vinod Govindapillai To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, vinod.govindapillai@intel.com, jani.nikula@intel.com, jani.saarinen@intel.com Subject: [PATCH v10 4/9] drm/i915/fbc: add register definitions for fbc dirty rect support Date: Fri, 28 Feb 2025 11:37:57 +0200 Message-ID: <20250228093802.27091-5-vinod.govindapillai@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250228093802.27091-1-vinod.govindapillai@intel.com> References: <20250228093802.27091-1-vinod.govindapillai@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Register definitions for FBC dirty rect support v2: - update to the patch subject Bspec: 71675, 73424 Reviewed-by: Ville Syrjälä Signed-off-by: Vinod Govindapillai --- drivers/gpu/drm/i915/display/intel_fbc_regs.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h index ae0699c3c2fe..b1d0161a3196 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h @@ -100,6 +100,15 @@ #define FBC_STRIDE_MASK REG_GENMASK(14, 0) #define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x)) +#define XE3_FBC_DIRTY_RECT(fbc_id) _MMIO_PIPE((fbc_id), 0x43230, 0x43270) +#define FBC_DIRTY_RECT_END_LINE_MASK REG_GENMASK(31, 16) +#define FBC_DIRTY_RECT_END_LINE(val) REG_FIELD_PREP(FBC_DIRTY_RECT_END_LINE_MASK, (val)) +#define FBC_DIRTY_RECT_START_LINE_MASK REG_GENMASK(15, 0) +#define FBC_DIRTY_RECT_START_LINE(val) REG_FIELD_PREP(FBC_DIRTY_RECT_START_LINE_MASK, (val)) + +#define XE3_FBC_DIRTY_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x43234, 0x43274) +#define FBC_DIRTY_RECT_EN REG_BIT(31) + #define ILK_FBC_RT_BASE _MMIO(0x2128) #define ILK_FBC_RT_VALID REG_BIT(0) #define SNB_FBC_FRONT_BUFFER REG_BIT(1) -- 2.43.0