From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8BB7BC35FFF for ; Thu, 20 Mar 2025 17:32:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 41BA510E678; Thu, 20 Mar 2025 17:32:18 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="O9hOa8jf"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id AEE0410E66D; Thu, 20 Mar 2025 17:32:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1742491937; x=1774027937; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=b7r3DAJilFke+aJ9rkxKmnp+paNTsW9vy8xPFp6Bpck=; b=O9hOa8jfobouAXA6RKnk9Ptc2IDRZStPnOd+BkBZPRDqpT1zlK+YgrGX 71MIci6P3YQqxR5FG+jj87uUL9iryi4YYaRY4XMaN+4IW7ROOxKwsRmMO xLvkhSESnBPuTeIcagsyVbKeCDx3rAkFxbkgvL2O+SV9Dszva55T1qphO tjAr+atFQuMmhgnmGWfq8SzHaEpsAgrlsfLkG044jEUSoSO5DTCL8RLTq jh5XvallRroj9ZqI1DHKYVb2FIp6P65czHh8qPwj7dSV6xDTNZWm/dEtV cMpzPd5Qjas1f3XPtedkp4tT6fakq5Istl6Q2in/DEkMIqEDonNCAI75P g==; X-CSE-ConnectionGUID: Ba9wgM6gSvePhf19QWS+rw== X-CSE-MsgGUID: dCSlk4WuSEyfVn317AwV6Q== X-IronPort-AV: E=McAfee;i="6700,10204,11379"; a="69095593" X-IronPort-AV: E=Sophos;i="6.14,262,1736841600"; d="scan'208";a="69095593" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Mar 2025 10:32:17 -0700 X-CSE-ConnectionGUID: fGp+2LemS/OuNnsWUWQYRQ== X-CSE-MsgGUID: No3+0oWrQyCgfAaF+jsMyg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,262,1736841600"; d="scan'208";a="123168400" Received: from oandoniu-mobl3.ger.corp.intel.com (HELO mwauld-desk.intel.com) ([10.245.244.226]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Mar 2025 10:32:15 -0700 From: Matthew Auld To: intel-xe@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org, =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Matthew Brost Subject: [PATCH 1/7] drm/gpusvm: fix hmm_pfn_to_map_order() usage Date: Thu, 20 Mar 2025 17:29:58 +0000 Message-ID: <20250320172956.168358-10-matthew.auld@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250320172956.168358-9-matthew.auld@intel.com> References: <20250320172956.168358-9-matthew.auld@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Handle the case where the hmm range partially covers a huge page (like 2M), otherwise we can potentially end up doing something nasty like mapping memory which potentially is outside the range, and maybe not even mapped by the mm. Fix is based on the xe userptr code, which in a future patch will directly use gpusvm, so needs alignment here. Reported-by: Thomas Hellström Signed-off-by: Matthew Auld Cc: Matthew Brost --- drivers/gpu/drm/drm_gpusvm.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_gpusvm.c b/drivers/gpu/drm/drm_gpusvm.c index 2451c816edd5..48993cef4a74 100644 --- a/drivers/gpu/drm/drm_gpusvm.c +++ b/drivers/gpu/drm/drm_gpusvm.c @@ -817,6 +817,27 @@ drm_gpusvm_range_alloc(struct drm_gpusvm *gpusvm, return range; } +/* + * To allow skipping PFNs with the same flags (like when they belong to + * the same huge PTE) when looping over the pfn array, take a given a hmm_pfn, + * and return the largest order that will fit inside the PTE, but also crucially + * accounting for the original hmm range boundaries. + */ +static unsigned int drm_gpusvm_hmm_pfn_to_order(unsigned long hmm_pfn, + unsigned long hmm_pfn_index, + unsigned long npages) +{ + unsigned long size; + + size = 1UL << hmm_pfn_to_map_order(hmm_pfn); + size -= (hmm_pfn & ~HMM_PFN_FLAGS) & (size - 1); + hmm_pfn_index += size; + if (hmm_pfn_index > npages) + size -= (hmm_pfn_index - npages); + + return fls(size) - 1; +} + /** * drm_gpusvm_check_pages() - Check pages * @gpusvm: Pointer to the GPU SVM structure @@ -875,7 +896,7 @@ static bool drm_gpusvm_check_pages(struct drm_gpusvm *gpusvm, err = -EFAULT; goto err_free; } - i += 0x1 << hmm_pfn_to_map_order(pfns[i]); + i += 0x1 << drm_gpusvm_hmm_pfn_to_order(pfns[i], i, npages); } err_free: @@ -1408,7 +1429,7 @@ int drm_gpusvm_range_get_pages(struct drm_gpusvm *gpusvm, for (i = 0, j = 0; i < npages; ++j) { struct page *page = hmm_pfn_to_page(pfns[i]); - order = hmm_pfn_to_map_order(pfns[i]); + order = drm_gpusvm_hmm_pfn_to_order(pfns[i], i, npages); if (is_device_private_page(page) || is_device_coherent_page(page)) { if (zdd != page->zone_device_data && i > 0) { -- 2.48.1