From: gareth.yu@intel.com
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: Gareth Yu <gareth.yu@intel.com>
Subject: [PATCH] drm/i915/display: Send DSI DCS commands with pipeline flush in High Speed
Date: Fri, 9 May 2025 10:13:27 +0800 [thread overview]
Message-ID: <20250509021327.649003-1-gareth.yu@intel.com> (raw)
From: Gareth Yu <gareth.yu@intel.com>
With all of the boundary conditions when streaming the commands B2B in our
validation (part of the reason we added the flush), the Flush effectively
serializes the transmission of each command enqueued within the command
dispatcher to one per V. Blank line which simplifies the behavior of the
High Speed Arbitration.
So, unless we absolutely have to burst these to the Sink, we should be using
the Pipeline Flush bit to serialize the commands.
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14247
Cc : Suraj Kandpal <suraj.kandpal@intel.com>
Cc : Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Gareth Yu <gareth.yu@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++--
drivers/gpu/drm/i915/display/icl_dsi_regs.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 402b7b2e1829..f91f27067768 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -191,12 +191,12 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
else
tmp &= ~PAYLOAD_PRESENT;
- tmp &= ~VBLANK_FENCE;
+ tmp &= ~(VBLANK_FENCE | LP_DATA_TRANSFER | PIPELINE_FLUSH);
if (enable_lpdt)
tmp |= LP_DATA_TRANSFER;
else
- tmp &= ~LP_DATA_TRANSFER;
+ tmp |= PIPELINE_FLUSH;
tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT);
diff --git a/drivers/gpu/drm/i915/display/icl_dsi_regs.h b/drivers/gpu/drm/i915/display/icl_dsi_regs.h
index d4845ac65acc..b601b7632339 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi_regs.h
+++ b/drivers/gpu/drm/i915/display/icl_dsi_regs.h
@@ -272,6 +272,7 @@
#define PAYLOAD_PRESENT (1 << 31)
#define LP_DATA_TRANSFER (1 << 30)
#define VBLANK_FENCE (1 << 29)
+#define PIPELINE_FLUSH (1 << 28)
#define PARAM_WC_MASK (0xffff << 8)
#define PARAM_WC_LOWER_SHIFT 8
#define PARAM_WC_UPPER_SHIFT 16
--
2.34.1
next reply other threads:[~2025-05-09 2:14 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-09 2:13 gareth.yu [this message]
2025-05-09 2:19 ` ✓ CI.Patch_applied: success for drm/i915/display: Send DSI DCS commands with pipeline flush in High Speed Patchwork
2025-05-09 2:19 ` ✗ CI.checkpatch: warning " Patchwork
2025-05-09 2:20 ` ✓ CI.KUnit: success " Patchwork
2025-05-09 2:29 ` ✓ CI.Build: " Patchwork
2025-05-09 2:31 ` ✓ CI.Hooks: " Patchwork
2025-05-09 2:32 ` ✓ CI.checksparse: " Patchwork
2025-05-09 3:15 ` ✓ Xe.CI.BAT: " Patchwork
2025-05-09 4:16 ` [PATCH] " Kandpal, Suraj
2025-05-09 4:22 ` Yu, Gareth
2025-05-09 7:22 ` Jani Nikula
2025-05-09 9:25 ` [PATCH] drm/i915/display: Enforce pipeline flush with DSI HS transfer gareth.yu
2025-05-09 9:51 ` Jani Nikula
2025-05-09 10:34 ` Yu, Gareth
2025-05-16 14:27 ` Jani Nikula
2025-05-09 9:31 ` ✓ CI.Patch_applied: success for drm/i915/display: Send DSI DCS commands with pipeline flush in High Speed (rev2) Patchwork
2025-05-09 9:31 ` ✓ CI.checkpatch: " Patchwork
2025-05-09 9:32 ` ✓ CI.KUnit: " Patchwork
2025-05-09 9:41 ` ✓ CI.Build: " Patchwork
2025-05-09 9:43 ` ✓ CI.Hooks: " Patchwork
2025-05-09 9:45 ` ✓ CI.checksparse: " Patchwork
2025-05-09 10:15 ` ✓ Xe.CI.BAT: " Patchwork
2025-05-09 15:50 ` ✗ Xe.CI.Full: failure for drm/i915/display: Send DSI DCS commands with pipeline flush in High Speed Patchwork
2025-05-09 21:56 ` ✗ Xe.CI.Full: failure for drm/i915/display: Send DSI DCS commands with pipeline flush in High Speed (rev2) Patchwork
2025-05-26 19:46 ` ✗ CI.Patch_applied: " Patchwork
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