From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 860CBC3ABC3 for ; Tue, 13 May 2025 05:19:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4731E10E52A; Tue, 13 May 2025 05:19:21 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="PvVWDBiw"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) by gabe.freedesktop.org (Postfix) with ESMTPS id C1C4A10E534; Tue, 13 May 2025 05:19:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747113557; x=1778649557; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ehGHkA3m9BhwcWAWYlRK7LIp+HjA7c8xUWxao09E+Kg=; b=PvVWDBiwzer7WdTrmjYY+BpOJhnqt4krevGTPZzCurM/YOX0pP7JpcJJ aKo40wNkDHVdP03QM3JlbUGxtNHt7ZvyEDj+Vyy+EaRq1TwUejAsuKOtF GJ77gXtCN8ZfiirEL+anuIvY8mb1fBM6JtzscrcElSkUYOqljXqKamvjd 6NFDv0N9yhUE1f6YdjvfytVevEkEoJ2WgL2yNC62i09gylrlpaTXI6ga6 hUjb3v78p3gSv9j79APEXxvCbRAbkN+X1SMtxtg1xzSyZR67Z0W4gTL7K XYVexuXWjnSOdmA0PjUkzD/zBnkt0NfZp8EbLRLA5mfSHWyQ8AbLX+2iA w==; X-CSE-ConnectionGUID: szkm7U67S1KHD5SfXz3blw== X-CSE-MsgGUID: Aq9ddN+FTSSbb7GIvJA8Ng== X-IronPort-AV: E=McAfee;i="6700,10204,11431"; a="51597880" X-IronPort-AV: E=Sophos;i="6.15,284,1739865600"; d="scan'208";a="51597880" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 May 2025 22:19:16 -0700 X-CSE-ConnectionGUID: mdx7p3GRTSO8+pWjVBr/AQ== X-CSE-MsgGUID: SvSYOh5DT/2fFSlgyFjflw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,284,1739865600"; d="scan'208";a="137506276" Received: from mgolanimitul-x299-ud4-pro.iind.intel.com ([10.190.239.114]) by orviesa006.jf.intel.com with ESMTP; 12 May 2025 22:19:15 -0700 From: Mitul Golani To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Cc: ankit.k.nautiyal@intel.com, ville.syrjala@intel.com Subject: [PATCH v5 15/17] drm/i915/vrr: Add function to check if DC Balance Possible Date: Tue, 13 May 2025 10:46:58 +0530 Message-ID: <20250513051700.507389-16-mitulkumar.ajitkumar.golani@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250513051700.507389-1-mitulkumar.ajitkumar.golani@intel.com> References: <20250513051700.507389-1-mitulkumar.ajitkumar.golani@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Add function to check if DC Balance possibile on requested PIPE and also validate along with DISPLAY_VER check. Signed-off-by: Mitul Golani Reviewed-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_vrr.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 3a5d29327d4d..cd14d7efb863 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -256,6 +256,22 @@ void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state) crtc_state->mode_flags |= I915_MODE_FLAG_VRR; } +static +int intel_vrr_dc_balance_possible(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + enum pipe pipe = crtc->pipe; + + /* + * FIXME: Currently Firmware supports DC Balancing on PIPE A + * and PIPE B. Account those limitation while computing DC + * Balance parameters. + */ + return (HAS_VRR_DC_BALANCE(display) && + ((pipe == PIPE_A) || (pipe == PIPE_B))); +} + static void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state) { -- 2.48.1