From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 227F9C54E65 for ; Wed, 21 May 2025 11:53:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5FF9D11B518; Wed, 21 May 2025 11:53:49 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="GRiZ8Khw"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) by gabe.freedesktop.org (Postfix) with ESMTPS id 20B1211B518; Wed, 21 May 2025 11:53:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1747828428; x=1779364428; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0eJ5s4f3vaycL5FphWjwXIa3y8oHBRPenuVbx+3dc38=; b=GRiZ8KhwuQXdi5et+vDGoT0qFodYQXmVVi4jX+o5u8FsVfzl13/mylyf 8tATvzmE+nftvSpIZhd0rNua+fb+XFjRS3dagV+LOKEwd+/fbmwTI+EGj QP0T1mcYG2b8OGMgjRLZFCtTKpd7AjqVu9wgKRR9YccQr6yREw0I8yTeG c86p1KwgzvlQRDjFdRiXbxSmbNHqYVQ0egvlP71gbFLgNKcaocnjH8NEk 3tOF3alwNLtdvln7yf7lEX1s1PJwTQ/IBr8m+R0aPTEm9y2zPvbAQWbLw s+sfykPqoHC4inkgwKCep8CrQOTDgSDmd44/zOEfNi9Xse4md2iGBRzwM g==; X-CSE-ConnectionGUID: o/bPGRIrQhC7I5FOzJuoLw== X-CSE-MsgGUID: rqCGHynDQJGfCATFyl0SbQ== X-IronPort-AV: E=McAfee;i="6700,10204,11440"; a="67217797" X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="67217797" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2025 04:53:47 -0700 X-CSE-ConnectionGUID: Ef0e3ZC0SXu23yUeK37HyA== X-CSE-MsgGUID: lHDIFsexSOKOpTc7Z6Q3jA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,303,1739865600"; d="scan'208";a="140452882" Received: from abityuts-desk.ger.corp.intel.com (HELO jhogande-mobl1..) ([10.245.244.119]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 May 2025 04:53:45 -0700 From: =?UTF-8?q?Jouni=20H=C3=B6gander?= To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Cc: =?UTF-8?q?Jouni=20H=C3=B6gander?= , Ankit Nautiyal Subject: [PATCH v4 04/12] drm/i915/alpm: Add PR_ALPM_CTL register definitions Date: Wed, 21 May 2025 14:53:11 +0300 Message-ID: <20250521115319.2380655-5-jouni.hogander@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250521115319.2380655-1-jouni.hogander@intel.com> References: <20250521115319.2380655-1-jouni.hogander@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" Add PR_ALPM_CTL register definition and bits for it. Bspec: 71014 Signed-off-by: Jouni Högander Reviewed-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_psr_regs.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index 795e6b9cc575..aad3ac5f502e 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -266,6 +266,16 @@ #define _PIPE_SRCSZ_ERLY_TPT_B 0x71074 #define PIPE_SRCSZ_ERLY_TPT(pipe) _MMIO_PIPE((pipe), _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B) +#define _PR_ALPM_CTL_A 0x60948 +#define PR_ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PR_ALPM_CTL_A) +#define PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU BIT(6) +#define PR_ALPM_CTL_RFB_UPDATE_CONTROL BIT(5) +#define PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE BIT(4) +#define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK REG_GENMASK(1, 0) +#define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1_OR_T2 REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 0) +#define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1 REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 1) +#define PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T2 REG_FIELD_PREP(PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_MASK, 2) + #define _ALPM_CTL_A 0x60950 #define ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A) #define ALPM_CTL_ALPM_ENABLE REG_BIT(31) -- 2.43.0