[PATCH] drm/xe/hwmon: fix uninitialised access in xe_hwmon_pcode_write_power_limit

[Qasim Ijaz <qasdev00@gmail.com>]

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val0/val1 are not initialised and are passed to xe_pcode_read():

    xe_hwmon_pcode_write_power_limit()
      └─▶ xe_pcode_read()
            └─▶ pcode_mailbox_rw()
                  └─▶ __pcode_mailbox_rw()

If __pcode_mailbox_rw fails, val0/val1 could be left
uninitialised leading to xe_hwmon_pcode_write_power_limit()
to access them via drm_dbg. Or an uninitialised val0/val1
could be dereferenced inside __pcode_mailbox_rw.

To fix zero-initialise them to avoid potential UB and 
propagate error on failure.

Fixes: 7596d839f622 ("drm/xe/hwmon: Add support to manage power limits though mailbox")
Signed-off-by: Qasim Ijaz <qasdev00@gmail.com>
---
 drivers/gpu/drm/xe/xe_hwmon.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 0d32e977537c..04acb47488a0 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -179,7 +179,7 @@ static int xe_hwmon_pcode_write_power_limit(const struct xe_hwmon *hwmon, u32 at
 					    u32 uval)
 {
 	struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe);
-	u32 val0, val1;
+	u32 val0 = 0, val1 = 0;
 	int ret = 0;
 
 	ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_POWER_SETUP,
@@ -190,9 +190,11 @@ static int xe_hwmon_pcode_write_power_limit(const struct xe_hwmon *hwmon, u32 at
 						  READ_PL_FROM_PCODE : READ_PL_FROM_FW),
 						  &val0, &val1);
 
-	if (ret)
+	if (ret) {
 		drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n",
 			channel, val0, val1, ret);
+		return ret;
+	}
 
 	if (attr == PL1_HWMON_ATTR)
 		val0 = uval;
-- 
2.39.5