From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 59B2CC61CE8 for ; Fri, 6 Jun 2025 12:06:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1BFEC10EA82; Fri, 6 Jun 2025 12:06:54 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=redhat.com header.i=@redhat.com header.b="QcT0sSrB"; dkim-atps=neutral Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by gabe.freedesktop.org (Postfix) with ESMTPS id D4EC410EA82 for ; Fri, 6 Jun 2025 12:06:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1749211612; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8c6ZwDHb3uYxtsAvJpFTLFi4+b+kzhB9wfsMrz7lsLA=; b=QcT0sSrB+2HtMm+XduE3vnogZpsTu0jn2fJaDrMnJ6cSArAEc9ZwryVszxDtYnhowhHMm6 V/RikQkOXBZ9FdqrH8NA0qrq+VH9Vcs3B6I0pXgSSpeN6YVznbxvFR3Uf1wtOv/8l5JZz/ XMBKHTRULszqokDPvuF4HQkcxlv0W7c= Received: from mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-169-deCbbWWaO527rQf_oRFE7w-1; Fri, 06 Jun 2025 08:06:46 -0400 X-MC-Unique: deCbbWWaO527rQf_oRFE7w-1 X-Mimecast-MFC-AGG-ID: deCbbWWaO527rQf_oRFE7w_1749211604 Received: from mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 76FD31956089; Fri, 6 Jun 2025 12:06:44 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.44.33.65]) by mx-prod-int-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 585D918002B5; Fri, 6 Jun 2025 12:06:38 +0000 (UTC) From: Jocelyn Falempe To: Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , David Airlie , Simona Vetter , Christian Koenig , Huang Rui , Matthew Auld , Matthew Brost , Maxime Ripard , Thomas Zimmermann , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v8 8/9] drm/i915/display: Add drm_panic support for 4-tiling with DPT Date: Fri, 6 Jun 2025 13:48:12 +0200 Message-ID: <20250606120519.753928-9-jfalempe@redhat.com> In-Reply-To: <20250606120519.753928-1-jfalempe@redhat.com> References: <20250606120519.753928-1-jfalempe@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.93 X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Alder Lake and later, it's not possible to disable tiling when DPT is enabled. So this commit implements 4-Tiling support, to still be able to draw the panic screen. Signed-off-by: Jocelyn Falempe --- .../gpu/drm/i915/display/intel_atomic_plane.c | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index ce5471bd3c43..8c422c6a7186 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -1297,6 +1297,25 @@ static unsigned int intel_ytile_get_offset(unsigned int width, unsigned int x, u return offset; } +static unsigned int intel_4tile_get_offset(unsigned int width, unsigned int x, unsigned int y) +{ + u32 offset; + unsigned int swizzle; + unsigned int width_in_blocks = DIV_ROUND_UP(width, 32); + + /* Block offset */ + offset = ((y / YTILE_HEIGHT) * width_in_blocks + (x / YTILE_WIDTH)) * YTILE_SIZE; + + x = x % YTILE_WIDTH; + y = y % YTILE_HEIGHT; + + /* bit order inside a block is y4 y3 x4 y2 x3 x2 y1 y0 x1 x0 */ + swizzle = (x & 3) | ((y & 3) << 2) | ((x & 0xc) << 2) | (y & 4) << 4 | + ((x & 0x10) << 3) | ((y & 0x18) << 5); + offset += swizzle * 4; + return offset; +} + static void intel_panic_flush(struct drm_plane *plane) { struct intel_plane_state *plane_state = to_intel_plane_state(plane->state); @@ -1342,6 +1361,7 @@ static unsigned int (*intel_get_tiling_func(u64 fb_modifier))(unsigned int width case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: case I915_FORMAT_MOD_4_TILED_BMG_CCS: case I915_FORMAT_MOD_4_TILED_LNL_CCS: + return intel_4tile_get_offset; case I915_FORMAT_MOD_X_TILED: case I915_FORMAT_MOD_Yf_TILED: case I915_FORMAT_MOD_Yf_TILED_CCS: -- 2.49.0