From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B7EF7C71157 for ; Wed, 18 Jun 2025 09:41:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7B5B310E7D8; Wed, 18 Jun 2025 09:41:38 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (1024-bit key; unprotected) header.d=redhat.com header.i=@redhat.com header.b="fGlilAjP"; dkim-atps=neutral Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1DB2510E7D8 for ; Wed, 18 Jun 2025 09:41:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1750239697; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=aWTTi8FZbYEDW5xiUYs3MEDmgqvF5cs/pip6jmk+Nrw=; b=fGlilAjPcK/XwBjh3MjEhisCsedeX65lQAOsVASCzaGLOJpTxhTXWi6XXQxkHZUZr91KCV W4vJsNizt19pm55UDdFZcFQ5wehjnWho2hkDzmZGvEF+8FxTaVqfTaacx5Rx0ZDjVUG7a8 gY5cHYGkrY16kSWbr3wlRGlTH8tmpB8= Received: from mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-557-9cm4Ya36MEKpJK4UZSDBcw-1; Wed, 18 Jun 2025 05:41:33 -0400 X-MC-Unique: 9cm4Ya36MEKpJK4UZSDBcw-1 X-Mimecast-MFC-AGG-ID: 9cm4Ya36MEKpJK4UZSDBcw_1750239691 Received: from mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.40]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 9A98B180028D; Wed, 18 Jun 2025 09:41:31 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.45.225.137]) by mx-prod-int-04.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id E3AEC19560A3; Wed, 18 Jun 2025 09:41:25 +0000 (UTC) From: Jocelyn Falempe To: Maarten Lankhorst , Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= , David Airlie , Simona Vetter , Christian Koenig , Huang Rui , Matthew Auld , Matthew Brost , Maxime Ripard , Thomas Zimmermann , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v10 10/10] drm/i915/psr: Add intel_psr2_panic_force_full_update Date: Wed, 18 Jun 2025 11:31:28 +0200 Message-ID: <20250618094011.238154-11-jfalempe@redhat.com> In-Reply-To: <20250618094011.238154-1-jfalempe@redhat.com> References: <20250618094011.238154-1-jfalempe@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.0 on 10.30.177.40 X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" When the panic handler is called, configure the psr to send the full framebuffer to the monitor, otherwise the panic screen is only partially visible. Signed-off-by: Jocelyn Falempe --- v8: * Added in v8 .../gpu/drm/i915/display/intel_atomic_plane.c | 7 +++++++ drivers/gpu/drm/i915/display/intel_psr.c | 20 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_psr.h | 2 ++ 3 files changed, 29 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 086195a11af9..82669367647a 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -58,6 +58,7 @@ #include "intel_fb.h" #include "intel_fb_pin.h" #include "intel_fbdev.h" +#include "intel_psr.h" #include "skl_scaler.h" #include "skl_universal_plane.h" #include "skl_watermark.h" @@ -1319,6 +1320,7 @@ static unsigned int intel_4tile_get_offset(unsigned int width, unsigned int x, u static void intel_panic_flush(struct drm_plane *plane) { struct intel_plane_state *plane_state = to_intel_plane_state(plane->state); + struct intel_crtc_state *crtc_state = to_intel_crtc_state(plane->state->crtc->state); struct intel_plane *iplane = to_intel_plane(plane); struct intel_display *display = to_intel_display(iplane); struct drm_framebuffer *fb = plane_state->hw.fb; @@ -1326,6 +1328,11 @@ static void intel_panic_flush(struct drm_plane *plane) intel_bo_panic_finish(intel_fb); + if (crtc_state->enable_psr2_sel_fetch) { + /* Force a full update for psr2 */ + intel_psr2_panic_force_full_update(display, crtc_state); + } + /* Flush the cache and don't disable tiling if it's the fbdev framebuffer.*/ if (intel_fb == intel_fbdev_framebuffer(display->fbdev.fbdev)) { struct iosys_map map; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 8bee2f592ae7..73bdc54d7831 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2889,6 +2889,26 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, return 0; } +void intel_psr2_panic_force_full_update(struct intel_display *display, + struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + u32 val = man_trk_ctl_enable_bit_get(display); + + /* SF partial frame enable has to be set even on full update */ + val |= man_trk_ctl_partial_frame_bit_get(display); + val |= man_trk_ctl_continuos_full_frame(display); + + /* Directly write the register */ + intel_de_write_fw(display, PSR2_MAN_TRK_CTL(display, cpu_transcoder), val); + + if (!crtc_state->enable_psr2_su_region_et) + return; + + intel_de_write_fw(display, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), 0); +} + void intel_psr_pre_plane_update(struct intel_atomic_state *state, struct intel_crtc *crtc) { diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index 0cf53184f13f..9b061a22361f 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -57,6 +57,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, struct intel_crtc *crtc); void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb, const struct intel_crtc_state *crtc_state); +void intel_psr2_panic_force_full_update(struct intel_display *display, + struct intel_crtc_state *crtc_state); void intel_psr_pause(struct intel_dp *intel_dp); void intel_psr_resume(struct intel_dp *intel_dp); bool intel_psr_needs_vblank_notification(const struct intel_crtc_state *crtc_state); -- 2.49.0